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Application of resist-profile-aware source optimization in 28 nm full chip optical proximity correction 被引量:1
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作者 Jun Zhu David Wei Zhang +6 位作者 Chinte Kuo Qing Wang Fang Wei Chenming Zhang Han Chen Daquan He Stephen D.Hsu 《Journal of Semiconductors》 EI CAS CSCD 2017年第7期83-88,共6页
As technology node shrinks, aggressive design rules for contact and other back end of line(BEOL)layers continue to drive the need for more effective full chip patterning optimization. Resist top loss is one of the m... As technology node shrinks, aggressive design rules for contact and other back end of line(BEOL)layers continue to drive the need for more effective full chip patterning optimization. Resist top loss is one of the major challenges for 28 nm and below technology nodes, which can lead to post-etch hotspots that are difficult to predict and eventually degrade the process window significantly. To tackle this problem, we used an advanced programmable illuminator(FlexRay) and Tachyon SMO(Source Mask Optimization) platform to make resistaware source optimization possible, and it is proved to greatly improve the imaging contrast, enhance focus and exposure latitude, and minimize resist top loss thus improving the yield. 展开更多
关键词 integrated circuits OPC source optimization lithography resist top loss
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