A 200 mV low leakage current subthreshold SRAM bitcell in a 130 nm CMOS process

A low leakage current subthreshold SRAM in 130 nm CMOS technology is proposed for ultra low voltage（200 mV） applications.Almost all of the previous subthreshold works ignore the leakage current in both active and standby modes.To minimize leakage,a self-adaptive leakage cut off scheme is adopted in the proposed design without any extra dynamic energy dissipation or performance penalty.Combined with buffering circuit and reconfigurable operation,the proposed design ensures both read and standby stability without deteriorating writability in the subthreshold region.Compared to the referenced subthreshold SRAM bitcell,the proposed bitcell shows：（1） a better critical state noise margin,and（2） smaller leakage current in both active and standby modes. Measurement results show that the proposed SRAM functions well at a 200 mV supply voltage with 0.13μW power consumption at 138 kHz frequency.

COMPUTATIONAL AND EXPERI-MENTAL STUDY ON TIP LEAKAGE VORTEX OF CIRCUMFERENTIAL SKEWED BLADES

In the steady operation condition, the experiments and the numerical simulations are used to investigate the tip leakage flow fields in three low pressure axial flow fans with three kinds of circumferential skewed rotors, including the radial rotor, the forward-skewed rotor and the back- ward-skewed rotor. The three-dimensional viscous flow fields of the fans are computed. In the experiments, the two-dimensional plane particle image velocimetry （PIV） system is used to measure the flow fields in the tip region of three different pitchwise positions of each fan. The results show that the computational results agree well with the experimental data in the flow field of the tip region of each fan. The tip leakage vortex core segments based on method of the eigenmode analysis can display clearly some characteristics of the tip leakage vortex, such as the origination position of tip leak- age vortex, the development of vortex strength, and so on. Compared with the radial rotor, the other two skewed rotors can increase the stability of the tip leakage vortex and the increment in the forward-skewed rotor is more than that in the backward-skewed one. Among the tip leakage vortices of the three rotors, the velocity of the vortex in the forward-skewed rotor is th6 highest in the circumferential direction and the lowest in the axial direction.

GROUND BOUNCING NOISE REDUCTION TECHNIQUE CONSIDERING WAKE-UP DELAY IN MTCMOS CIRCUITS

Multi-Threshold CMOS(MTCMOS) is an effective technique for controlling leakage power with low delay overhead.However the large magnitude of ground bouncing noise induced by the sleep to active mode transition may cause signal integrity problem in MTCMOS circuits.We propose a methodology for reducing ground bouncing noise under the wake-up delay constraint.An improved two-stage parallel power gating structure that can suppress the ground bouncing noise through turn on sets of sleep transistors consecutively is proposed.The size of each sleep transistor is optimized by a novel sizing algorithm based on a simple discharging model.Simulation results show that the proposed techniques achieve at least 23% improvement in the product of the peak amplitude of ground bouncing noise and the wake-up time when compared with other existing techniques.

Improved device performance of recessed-gate AlGaN/GaN HEMTs by using in-situ N_(2)O radical treatment

The N_(2)O radicals in-situ treatment on gate region has been employed to improve device performance of recessedgate Al Ga N/Ga N high-electron-mobility transistors(HEMTs).The samples after gate recess etching were treated by N_(2)O radicals without physical bombardment.After in-situ treatment(IST)processing,the gate leakage currents decreased by more than one order of magnitude compared to the sample without IST.The fabricated HEMTs with the IST process show a low reverse gate current of 10;A/mm,high on/off current ratio of 108,and high f_(T)×L_(g)of 13.44 GHz·μm.A transmission electron microscope(TEM)imaging illustrates an oxide layer with a thickness of 1.8 nm exists at the AlGaN surface.X-ray photoelectron spectroscopy(XPS)measurement shows that the content of the Al-O and Ga-O bonds elevated after IST,indicating that the Al-N and Ga-N bonds on the AlGaN surface were broken and meanwhile the Al-O and Ga-O bonds formed.The oxide formed by a chemical reaction between radicals and the surface of the AlGaN barrier layer is responsible for improved device characteristics.

Gate leakage current reduction in IP3 SRAM cells at 45 nm CMOS technology for multimedia applications

We have presented an analysis of the gate leakage current of the IP3 static random access memory （SRAM） cell structure when the cell is in idle mode（performs no data read/write operations） and active mode （performs data read/write operations）,along with the requirements for the overall standby leakage power,active write and read powers.A comparison has been drawn with existing SRAM cell structures,the conventional 6T,PP, P4 and P3 cells.At the supply voltage,V_（DD） = 0.8 V,a reduction of 98%,99%,92%and 94%is observed in the gate leakage current in comparison with the 6T,PP,P4 and P3 SRAM cells,respectively,while at V_（DD） = 0.7 V,it is 97%,98%,87%and 84%.A significant reduction is also observed in the overall standby leakage power by 56%〉, the active write power by 44%and the active read power by 99%,compared with the conventional 6T SRAM cell at V_（DD）= 0.8 V,with no loss in cell stability and performance with a small area penalty.The simulation environment used for this work is 45 nm deep sub-micron complementary metal oxide semiconductor（CMOS） technology,t_（ox） = 2.4 nm,K_（thn） = 0.22 V,K_（thp） = 0.224 V,V_（DD） = 0.7 V and 0.8 V,at T = 300 K.

A boosted negative bit-line SRAM with write-assisted cell in 45 nm CMOS technology

A new 11 T SRAM cell with write-assist is proposed to improve operation at low supply voltage. In this technique, a negative bit-line voltage is applied to one of the write bit-lines, while a boosted voltage is applied to the other write bit-line where transmission gate access is used in proposed 11 T cell. Supply voltage to one of the inverters is interrupted to weaken the feedback. Improved write feature is attributed to strengthened write access devices and weakened feedback loop of cell at the same time. Amount of boosting required for write performance improvement is also reduced due to feedback weakening, solving the persistent problem of half-selected cells and reliability reduction of access devices with the other suggested boosted and negative bit-line techniques. The proposed design improves write time by 79%, 63% and slower by 52% with respect to LP 10 T, WRE 8 T and 6 T cells respectively. It is found that write margin for the proposed cell is improved by about 4×, 2.4× and 5.37× compared to WRE8 T, LP10 T and 6 T respectively. The proposed cell with boosted negative bit line（BNBL） provides47%, 31%, and 68.4% improvement in write margin with respect to no write-assist, negative bit line（NBL） and boosted bit line（BBL） write-assist respectively. Also, new sensing circuit with replica bit-line is proposed to give a more precise timing of applying boosted voltages for improved results. All simulations are done on TSMC 45 nm CMOS technology.

6T SRAM cell analysis for DRV and read stability

The present paper analyzes the hold and read stability with temperature and aspect ratio variations. To reduce the power dissipation, one of the effective techniques is the supply voltage reduction. At this reduced supply voltage the data must be stable. So, the minimum voltage should be discovered which can also retain the data. This voltage is the data retention voltage（DRV）. The DRV for 6T SRAM cell is estimated and analyzed in this paper.The sensitivity analysis is performed for the DRV variation with the variation in the temperature and aspect ratio of the pull up and pull down transistors. Cadence Virtuoso is used for DRV analysis using 45 nm GPDK technology files. After this, the read stability analysis of 6T SRAM cell in terms of SRRV（supply read retention voltage） and WRRV（wordline read retention voltage） is carried out. Read stability in terms of RSNM can be discovered by accessing the internal storage nodes. But in the case of dense SRAM arrays instead of using internal storage nodes,the stability can be discovered by using direct bit line measurements with the help of SRRV and WRRV. SRRV is used to find the minimum supply voltage for which data can be retained during a read operation. Similarly, WRRV is used to find the boosted value of wordline voltage, for which data can be retained during read operation. The SRRV and WRRV values are then analyzed for different Cell Ratios. The results of SRRV and WRRV are then compared with the reported data for the validation of the accuracy of the results.