Low Phase Noise LC-VCO with Multi-stage Filtering

A low-phase-noise CMOS voltage-controlled oscillator( VCO) with zero-bias scheme and multi-stage filtering is presented. Sharing ground w ith fully integrated loop filter,the PM OS-only VCO achieves a zero-bias scheme,w hich prevents tuning line noise from disturbing VCO output common-mode voltage and hence minimizes phase noise caused by nonlinear C-V characteristic of varactors. Top-biased current source is optimized by multi-stage filtering to reduce 1/f flicker and thermal noise. Fabricated in TSM C 180 nm CM OS process,the proposed VCO exhibits a measured oscillation frequency of 0.85 ~ 1.45 GHz,w ith a phase noise of-121.8 ^-131.3 dBc/Hz @ 1MHz offset over the w hole band. Pow er consumption is 3.8 ~ 6.3 mW from a 1.8 V supply.

A wideband low-phase-noise LC VCO for DRM/DAB frequency synthesizer

The wideband CMOS voltage-controlled oscillator（VCO）with low phase noise and low power consumption is presented for a DRM/DAB（digital radio mondiale and digital audio broadcasting）frequency synthesizer.In order to obtain a wide band and a large tuning range,a parallel switched capacitor bank is added in the LC tank.The proposed VCO is implemented in SMIC 0.18-μm RF CMOS technology and the chip area is 750 μm×560 μm,including the test buffer circuit and the pads.Measured results show that the tuning range is 44.6%;i.e.,the frequency turning range is from 2.27 to 3.57 GHz.The measured phase noise is-122.22 dBc/Hz at a 1 MHz offset from the carrier.The maximum power consumption of the core part is 6.16 mW at a 1.8 V power supply.

A wideband low power low phase noise dual-modulus prescaler

This paper describes a novel divide-by-32/33 dual-modulus prescaler （DMP）. Here, a new combination of DFF has been introduced in the DMP. By means of the cooperation and coordination among three types, DFF, SCL, TPSC, and CMOS static flip-flop, the DMP demonstrates high speed, wideband, and low power consumption with low phase noise. The chip has been fabricated in a 0.18μm CMOS process of SMIC. The measured results show that the DMP＇s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier. The core area of the die without PAD is 57 x 30 #m2. Due to its excellent performance, the DMP could be applied to a PLL-based frequency synthesizer for many RF systems, especially for multi-standard radio applications.

A 4.2-5GHz,low phase noise LC-VCO with constant bandwidth and small tuning gain

As the tuning frequency of an integrated LC-voltage controlled oscillator （LC-VCO） increases, it is difficult to co-design the active negative resistance core and the varactor to achieve wideband frequency range, low phase noise, constant bandwidth and small tuning gain together. The presented VCO solves the problem by designing a set of changeable varactor units. The whole VCO was implemented in a 0.18μm CMOS process. The measured result shows -120 dBc/Hz phase noise at 1 MHz offset. The measured tuning range is from 4.2 to 5 GHz and the tuning gain is 8-10 MHz/V. The VCO draws 4 mA from a 1.5 V supply voltage.

A wide-band low phase noise LC-tuned VCO with constant K_(VCO)/ω_(osc) for LTE PLL

A wideband LC-tuned voltage-controlled oscillator（LC-VCO） applied in LTE PLL frequency synthesizers with constant AVco/ωosc is described.In order to minimize the loop bandwidth variations of PLL,a varactor array is proposed,which consists of a series of differential variable capacitor pairs and a series of single-pole double-throw（SPDT） switches to connect Vtune or Vdd.The switches are controlled by switching bits.With this scheme,the ratio of KV =（？）Cvar/（？）Vtune and the capacitance value of the capacitor array maintains relatively constant; furthermore,the loop bandwidth of the PLL fluctuation is suppressed.The 3.2—4.6-GHz VCO for multi-band LTE PLL is fabricated in a 0.13-μm RF-CMOS process.The VCO exhibits a maximum variation of AVCO/ωosc of only±4%.The VCO also exhibits a low phase-noise of-124 dBc/Hz at a 1-MHz offset frequency and a low current consumption of 18.0 mA with a 1.2-V power supply.

Low phase noise and quasi-tunable millimeter-wave generator using a passively In As/InP mode-locked quantum dot laser

A low phase noise millimeter-wave(MMW) signal generator is proposed and experimentally demonstrated with a C-band passively Fabry-Pérot(F-P) quantum dot mode-locked laser. A novel method is proposed to generate low phase noise MMW signal, which is simply based on a commercial off-the-shelf dual-driven Li Nb O3 Mach-Zehnder modulator and a passively F-P quantum dot mode-locked laser. MMW signal with the frequency of 30 GHz, 45 GHz and 90 GHz respectively is obtained experimentally. Single-sideband phase noise of the 30 GHz and 45 GHz MMW signal is-112 d Bc/Hz and-106 d Bc/Hz at an offset of 1 k Hz, respectively. The linewidth of the 30 GHz and 45 GHz MMW signal is about from 225 Hz and 239 Hz. This is considered a very simple MMW generator with a quasi-tunable broadband and ultra-low phase noise.

A 6 GHz high power and low phase noise VCO using an InGaP/GaAs HBT

A 6 GHz voltage controlled oscillator （VCO） optimized for power and noise performance was designed and characterized. This VCO was designed with the negative-resistance （Neg-R） method, utilizing an InGaP/GaAs hetero-junction bipolar transistor in the negative-resistance block. A proper output matching network and a high Q stripe line resonator were used to enhance output power and depress phase noise. Measured central frequency of the VCO was 6.008 GHz. The tuning range was more than 200 MHz. At the central frequency, an output power of 9.8 dBm and phase noise of-122.33 dBc/Hz at 1 MHz offset were achieved, the calculated RF to DC efficiency was about 14%, and the figure of merit was -179.2 dBc/Hz.

A fully integrated CMOS VCXO-IC with low phase noise, wide tuning range and high tuning linearity

This paper describes a low phase noise, wide tuning range and high tuning linearity CMOS voltage controlled crystal oscillator IC （VCXO-IC） with LVCMOS and LVPECL output. A differential coupled frequency doubling Colpitts oscillator is adopted to obtain low noise 2x frequency output. Wide tuning range and high lin- earity are simultaneously achieved by using MOS varactor arrays. The measurement results show that the designed VCXO-IC achieves -134 dBc/Hz phase noise at 1 kHz offset frequency and 4-135 ppm output frequency tuning range within 3% linearity by using 40 MHz fundamental AT-cut crystal. The VCXO-IC is fabricated in the chartered 0.35/zm standard CMOS process and occupies a total silicon area of 2.4 mm2.

A novel wideband low phase noise 2:1 frequency divider

This paper describes a novel low-power wideband low-phase noise divide-by-two frequency divider. Hereby,a new D-latch topology is introduced.By means of conventional dynamic source-coupled logic techniques, the divider demonstrates a wideband with low phase noise by adding a switch transistor between the clock port and the couple node of the input NMOS pair in the D latch.The chip was fabricated in the 90-nm CMOS process of IBM.The measurement results show that the frequency divider has an input frequency range from 0.05 to 10 GHz and the phase noise is-159.8 dBc/Hz at 1 MHz offset from the carrier.Working at 10 GHz,the frequency divider dissipates a total power of 9.12 mW from a 1.2 V supply while occupying only 0.008 mm~2 of the core die area.

A 0.8 V low power low phase-noise PLL

A low power and low phase noise phase-locked loop（PLL） design for low voltage（0.8 V） applications is presented.The voltage controlled oscillator（VCO） operates from a 0.5 V voltage supply,while the other blocks operate from a 0.8 V supply.A differential NMOS-only topology is adopted for the oscillator,a modified precharge topology is applied in the phase-frequency detector（PFD）,and a new feedback structure is utilized in the charge pump（CP） for ultra-low voltage applications.The divider adopts the extended true single phase clock DFF in order to operate in the high frequency region and save circuit area and power.In addition,several novel design techniques,such as removing the tail current source,are demonstrated to cut down the phase noise.Implemented in the SMIC 0.13μm RF CMOS process and operated at 0.8 V supply voltage,the PLL measures a phase noise of-112.4 dBc/Hz at an offset frequency of 1 MHz from the carrier and a frequency range of 3.166-3.383 GHz.The improved PFD and the novel CP dissipate 0.39 mW power from a 0.8 V supply.The occupied chip area of the PFD and CP is 100×100μm^2.The chip occupies 0.63 mm^2,and draws less than 6.54 mW from a 0.8 V supply.

A 220–1100 MHz low phase-noise frequency synthesizer with wide-band VCO and selectable I/Q divider

This paper presents a low phase-noise fractional-N frequency synthesizer which provides an inphase/quadrature-phase（I/Q） signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation（WIA） applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator（VCO） is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 k Hz loop bandwidth, lowest measured phase noise is 106 dBc/Hz at a 10 k Hz offset and 131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm^2, consumes only 15 m W from the 1.8 V power supply,and settles within 13.2 s. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.

Design and realization of an ultra-low-power low-phase-noise CMOS LC-VCO

A fully integrated cross-coupled LC tank voltage-controlled oscillator（LC-VCO） using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μm CMOS technology of SMIC. The measured phase noise is-125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz,while the VCO core circuit draws only 640μW from a 0.4-V supply.The designed VCO can cover a frequency range from 2.28 to 2.48 GHz.The tuning range of the circuit is 200 MHz（8.7%） and the FOM is-195.7 dB,which is suitable for an IEEE 802.11b receiver.

Frequency synthesizer for DRM/DAB/AM/FM RF front-end

This paper describes a wideband low phase noise frequency synthesizer.It operates in the multi-band including digital radio mondiale DRM digital audio broadcasting DAB amplitude modulation AM and frequency modulation FM .In order to cover the signals of the overall frequencies a novel frequency planning and a new structure are proposed. A wide-band low-phase-noise low-power voltage-control oscillator VCO and a high speed wide band high frequency division ratio pulse swallow frequency divider with a low power consumption are presented.The monolithic DRM/DAB/AM/FM frequency synthesizer chip is also fabricated in a SMIC＇s 0.18-μm CMOS process.The die area is 1 425 μm ×795 μm including the test buffer and pads. The measured results show that the VCO operating frequency range is from 2.22 to 3.57 GHz the measured phase noise of the VCO is 120.22 dBc/Hz at 1 MHz offset the pulse swallow frequency divider operation frequency is from 0.9 to 3.4 GHz.The phase noise in the phase-locked loop PLL is-59.52 dBc/Hz at 10 kHz offset and fits for the demand of the DRM/DAB/AM/FM RF front-end. The proposed frequency synthesizer consumes 47 mW including test buffer under a 1.8 V supply.

Monolithic CEO-stabilization scheme-based frequency comb from an octave-spanning laser

We demonstrate a carder-envelope phase-stabilized octave-spanning oscillator based on the monolithic scheme. A wide output spectrum extending from 480 nm to 1050 nm was generated directly from an all-chirped mirror Ti：sapphire laser. After several improvements, the carder-envelope offset （CEO） beat frequency accessed nearly 60 dB under a reso- lution of 100 kHz. Using a feedback system with 50-kHz bandwidth, we compressed the residual phase noise to 55 mrad （integrated from 1 Hz to 1 MHz） for the stabilized CEO, corresponding to 23-as timing jitter at the central wavelength of 790 nm. This is, to the best of our knowledge, the smallest timing jitter achieved among the existing octave-spanning laser based frequency combs.

A low power CMOS VCO using inductive-biasing with high performance FoM

A novel voltage-controlled oscillator（VCO） topology with low voltage and low power is presented. It employed the inductive-biasing to build a feedback path between the tank and the MOS gate to enhance the voltage gain from output nodes of the tank to the gate node of the cross-coupled transistor. Theoretical analysis using timevarying phase noise theory derives closed-form symbolic formulas for the 1/f^2 phase noise region, showing that this feedback path could improve the phase noise performance. The proposed VCO is fabricated in TSMC 0.13 m CMOS technology. Working under a 0.3 V supply voltage with 1.2 m W power consumption, the measured phase noise of the VCO is –119.4 d Bc/Hz at 1 MHz offset frequency from the carrier of 4.92 GHz, resulting in an Fo M of 192.5 d Bc/Hz.

Design and analysis of a three-stage voltage-controlled ring oscillator

This paper describes a large tuning range low phase noise voltage-controlled ring oscillator （ring VCO） based on a different cascade voltage logic delay cell with current-source load to change the current of output node. The method for optimization is presented. Furthermore, the analysis of performance of the proposed ring VCO is confirmed by the measurement results. The three-stage proposed ring VCO was fabricated in the 180-nm CMOS process of SMIC. The measurement results show that the oscillator frequency of the ring VCO is from 0.77O to 5.286 GHz and the phase noise is 97.93 dBc/Hz at an offset of 1 MHz from 5.268 GHz with a total power of 15.1 mW from a 1.8 V supply while occupying only 0.00175 mm2 of the core die area.