This paper presents the design and implementation of a low power digital signal processor(THUCID-SP-1)targeting at application for cochlear implants.Multi-level low power strategies including algorithmoptimization,ope...This paper presents the design and implementation of a low power digital signal processor(THUCID-SP-1)targeting at application for cochlear implants.Multi-level low power strategies including algorithmoptimization,operand isolation,clock gating and memory partitioning are adopted in the processor designto reduce the power consumption.Experimental results show that the complexity of the Continuous Inter-leaved Sampling(CIS)algorithm is reduced by more than 80% and the power dissipation of the hardwarealone is reduced by about 25% with the low power methods.The THUCIDSP-l prototype,fabricated in0.18-μm standard CMOS process,consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.展开更多
A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very la...A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.展开更多
介绍了基于瞬时无功功率理论的ip-iq谐波检测方法及对低通滤波器的要求,分析讨论了数字低通滤波器的类型、阶数及截止频率对有源电力滤波器谐波检测效果的影响。利用Matlab仿真软件设计了二阶巴特沃思(Butterworth)数字低通滤波器,对ip...介绍了基于瞬时无功功率理论的ip-iq谐波检测方法及对低通滤波器的要求,分析讨论了数字低通滤波器的类型、阶数及截止频率对有源电力滤波器谐波检测效果的影响。利用Matlab仿真软件设计了二阶巴特沃思(Butterworth)数字低通滤波器,对ip-iq谐波检测算法进行了仿真研究,并结合TI公司推出的浮点算法在定点DSP上实现的函数库-IQ math Library,完成了ip-iq谐波检测方法在TMS320F2812DSP中的实现,并取得良好的实验效果。展开更多
针对当前安防领域里防毒面具不易进行有效通信问题,设计一种用于防毒面具的无线通话系统。以抗干扰、低功耗和耐高低温三因素为基准,声源经过EFM32系列MCU、BR261系列DSP和TP2015D1音频放大器处理,最终输出高质量的音频信号。通过LeCro...针对当前安防领域里防毒面具不易进行有效通信问题,设计一种用于防毒面具的无线通话系统。以抗干扰、低功耗和耐高低温三因素为基准,声源经过EFM32系列MCU、BR261系列DSP和TP2015D1音频放大器处理,最终输出高质量的音频信号。通过LeCroy示波器波形分析表明,该系统可识别人声和呼吸气流声,最大工作电流I_(mean)<200 m A,关闭声源放大器时最大电流I_(max)<30 m A,满足低功耗工作要求,声源输出稳定清晰,具备一定抗静电强磁干扰能力。展开更多
基金Supported by the National Natural Science Foundation of China (No. 60475018)
文摘This paper presents the design and implementation of a low power digital signal processor(THUCID-SP-1)targeting at application for cochlear implants.Multi-level low power strategies including algorithmoptimization,operand isolation,clock gating and memory partitioning are adopted in the processor designto reduce the power consumption.Experimental results show that the complexity of the Continuous Inter-leaved Sampling(CIS)algorithm is reduced by more than 80% and the power dissipation of the hardwarealone is reduced by about 25% with the low power methods.The THUCIDSP-l prototype,fabricated in0.18-μm standard CMOS process,consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.
基金supported by the National Natural Science Foundation of China under Grant No.90407007University Science Foundation of China under Grant No R0820207
文摘A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.
文摘介绍了基于瞬时无功功率理论的ip-iq谐波检测方法及对低通滤波器的要求,分析讨论了数字低通滤波器的类型、阶数及截止频率对有源电力滤波器谐波检测效果的影响。利用Matlab仿真软件设计了二阶巴特沃思(Butterworth)数字低通滤波器,对ip-iq谐波检测算法进行了仿真研究,并结合TI公司推出的浮点算法在定点DSP上实现的函数库-IQ math Library,完成了ip-iq谐波检测方法在TMS320F2812DSP中的实现,并取得良好的实验效果。
文摘针对当前安防领域里防毒面具不易进行有效通信问题,设计一种用于防毒面具的无线通话系统。以抗干扰、低功耗和耐高低温三因素为基准,声源经过EFM32系列MCU、BR261系列DSP和TP2015D1音频放大器处理,最终输出高质量的音频信号。通过LeCroy示波器波形分析表明,该系统可识别人声和呼吸气流声,最大工作电流I_(mean)<200 m A,关闭声源放大器时最大电流I_(max)<30 m A,满足低功耗工作要求,声源输出稳定清晰,具备一定抗静电强磁干扰能力。
