Ultra-Low Power Designing for CMOS Sequential Circuits

Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold vol-tages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 - 200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

Design of a Low Power DSP with Distributed and Early Clock Gating

A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.

Design of Low-Power Data Logger of Deep Sea for Long-Term Field Observation

This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors （pH electrode, H2S electrode, H2 electrode） and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.

A vector inserting TPG for BIST design with low peak power consumption

A test pattern generator （TPG） which can highly reduce the peak power consumption during built-in self-test （BIST） application is proposed. The proposed TPG, called LPpe-TPG, consists of a linear feedback shift register （LFSR） and some control circuits. A procedure is presented firstly to make compare vectors between pseudorandom test patterns by adding some circuits to the original LFSR and secondly to insert some vectors between two successive pseudorandom test patterns according to the ordinal selection of every two bits of the compare vector. Then the changes between any successive test patterns of the test set generated by the LPpe-TPG are not more than twice. This leads to a decrease of the weighted switching activity （WSA） of the circuit under test （CUT） and therefore a reduction of the power consumption. Experimental results based on some ISCAS＇ 85 benchmark circuits show that the peak power consumption has been reduced by 25.25% to 64.46%. Also, the effectiveness of our approach to reduce the total and average power consumption is kept, without losing stuck-at fault coverage.

A Low-Power-Consumption 9bit 10MS/s Pipeline ADC for CMOS Image Sensors

A low-power-consumption 9bit 10MS/s pipeline ADC,used in a CMOS image sensor,is proposed. In the design, the decrease of power consumption is achieved by applying low-power-consumption and large-output-swing amplifiers with gain boost structure, and biasing all the cells with the same voltage bias source, which requires careful layout design and large capacitors. In addition,capacitor array DAC is also applied to reduce power consumption,and low threshold voltage MOS transistors are used to achieve a large signal processing range. The ADC was implemented in a 0.18μm 4M-1 P CMOS process,and the experimental results indicate that it consumes only 7mW, which is much less than general pipeline ADCs. The ADC was used in a 300000 pixels CMOS image sensor.

Design and Implement of Low Power Consumption SRAM Based on Single Port Sense Amplifier in 65 nm

With the rapid development of integrated circuits [1], low power consumption has become a constant pursuiting goal of the designer in chip design. As the memory almost takes up the area of the chip, reducing memory power consumption will significantly reduce the overall power consumption of the chip;according to ISSCC’s 2014 report about technology trends discussions, there two points of the super-low power SRAM design: 1) design a more effective static and dynamic power control circuit for each key module of SRAM;2) ensure that in the case of the very low VDD min, SRAM can operating reliably and stably. This paper makes full use reliable of 8T cell, and the single-port sense amplifier has solved problems in the traditional 8T cell structure, making the new structure of the memory at a greater depth still maintain good performance and lower power consumption. Compared with the designed SRAM the SRAM generated by commercial compiler, as the performance loss at SS corner does not exceed 10%, the whole power consumption could be reduced by 54.2%, which can achieve a very good effect of low-power design.

Low Power Transceiver Design Parameters for Wireless Sensor Networks

Designing low power sensor networks has been the general goal of design engineers, scientist and end users. It is desired to have a wireless sensor network (WSN) that will run on little power (if possible, none at all) thereby saving cost, and the inconveniences of having to replace batteries in some difficult to access areas of usage. Previous researches on WSN energy models have focused less on the aggregate transceiver energy consumption models as compared to studies on other components of the node, hence a large portion of energy in a WSN still get depleted through data transmission. By studying the energy consumption map of the transceiver of a WSN node in different states and within state transitions, we propose in this paper the energy consumption model of the transceiver unit of a typical sensor node and the transceiver design parameters that significantly influences this energy consumption. The contribution of this paper is an innovative energy consumption model based on simple finite automata which reveals the relationship between the aggregate energy consumption and important power parameters that characterize the energy consumption map of the transceiver in a WSN;an ideal tool to design low power WSN.

Design for Low Power Testing of Computation Modules with Contiguous Subspace in VLSI

A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

SYNCHRONOUS DERIVED CLOCK AND SYNTHESIS OF LOW POWER SEQUENTIAL CIRCUITS

Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.

嵌入式机房多功能模块智能监控系统设计

为充分提高大型机房智能化运维能力,及时排除各种异常情况,实现高精度、低功耗的系统设计目标;提出基于嵌入式的机房多功能模块智能监控系统设计方法;设计针对机房空间的传感信号采集层、数据传输层、后台监控层的多层系统架构;硬件结构设计了用户登录模块、传感器运行模块、数据记录模块和监控显示模块,4个功能模块在多层架构下工作;软件部分通过数据传输程序连接终端设备与云计算中心,利用数据处理程序完成功能模块参数设置,完成嵌入式机房运行数据自动监控,针对系统的功耗问题,设计了微结构级功耗模型,降低系统功耗;实验结果表明:所设计系统容错率在80%以上,数据采集精度高,当浓度超过100 ppm时,自动对烟雾超标情况启动报警装置;可以实时响应接入设备,及时获取预警信息,功耗低,平均响应时间均在2.8 s以下,实现嵌入式机房自动智能监控。

存储体编译和布局协同的片上缓存设计方法

为了提高片上缓存的速度、降低面积和功耗,提出了一种存储体编译和布局协同的片上缓存设计方法。该方法基于存储体在芯片上的不同空间位置预估该存储体的时序余量,分别采用拆分/合并、尺寸调整、阈值替换和长宽比变形等多种配置参数穷举组合进行存储体编译,根据时序余量选择最优的静态随机存取存储器存储体编译配置。将该方法与现有的物理设计步骤集成为一个完整的设计流程。实验结果表明,该方法能够降低约9.9%的功耗,同时缩短7.5%的关键路径延时。

铁路系统中传感器的低功耗电源管理系统设计

探讨铁路系统中无线传感器的低功耗电源管理策略,并提出一种创新的改进策略。先介绍了铁路传感器系统的架构和相关的能源管理电路设计,然后分析了系统的状态转换过程,包括状态切换时间点和功耗问题。基于这些分析,提出一种自适应功耗模块激活策略,该策略根据传感器传输数据的频率和重要性来动态调整功耗模块的激活频率。此外,还研究了基于状态切换的功率优化方法,以最大限度地减小功率消耗。

城轨14号道岔轨道刚度规律及低动力设计

为研究侧向过岔速度更高的国产14号无砟道岔轨道刚度分布规律,基于有限元理论,建立城轨14号道岔轨道刚度计算模型,模型中充分考虑轨下胶垫、板下胶垫、钢轨类型、滑床台等部件的影响,重点分析了14号道岔整体刚度纵向分布的变化规律,并针对轨道刚度分布不均匀进行了低动力设计。结果表明:城轨14号单开道岔轨道竖向刚度沿线路纵向不均匀分布,其中连接部分刚度最小,转辙器部分刚度最大值为连接部分的1.5倍,辙叉部分刚度最大值为连接部分的2.0倍;通过低动力设计,钢轨整体刚度纵向变化率最大值从207.4%降至121.6%,钢轨挠度变化率全部降至0.3 mm/m以内,能够满足城轨14号道岔的运输组织要求。

适用于海洋动态观测设备嵌入式系统的低功耗管理预测模型

能耗是制约海洋设备在水下工作时长的关键因素。为进一步降低海洋动态观测设备嵌入式系统的动态功耗,本文针对前人提出的用于预测空闲时间的指数平滑算法所存在的权重系数基于凑数法确定、算法难以适应大波动等问题,设计了一种新的权重系数,并构建了一种自适应的低功耗管理预测模型。当模型检测到预测的空闲时间超过工作和休眠状态切换的时间阈值后,中央处理器关停系统的部分外设,使系统进入低功耗休眠状态。仿真和单片机实验均表明,本文提出的低功耗管理预测模型能够有效地提高对处理器工作的空闲时间预测的准确性,且面对突发状况具有良好的自适应性,可显著降低嵌入式系统的功耗,有效延长设备的工作时间。

混合集成YIG频率合成器设计

将YIG振荡电路与控制单元、锁相单元进行混合集成制作频率合成器。首先介绍了YIG频率合成器的基本原理,在此基础上提出了混合集成的设计思路和具体设计措施。重点提出采用“永磁偏置”和“无加热器”方案降低体积和功耗,采用“均磁”措施提升磁场均匀性,采用YIG小球与永磁体互补法降低频率温漂,实现了YIG频率合成器的小型化和低功耗设计。其体积较常规YIG频率合成器减小约2/3,功耗仅约3.6 W,相位噪声性能与常规YIG频率合成器相当。最后指出了这种混合集成一体化结构设计的适用性,即混合集成一体化结构设计思想不仅适用于YIG频率合成器,也适用于多功能YIG滤波组件的集成化设计,但也存在不足和局限性。

一种可暂停的低功耗DMA控制器设计及验证

通过分析直接内存存取(DMA)控制器的工作原理和主要功耗来源,发现其在空闲状态时依然存在功耗较高的问题,为了解决空闲状态功耗损失问题以及满足DMA控制器实际传输过程中可能出现的暂停需求,提出了一种可暂停的低功耗DMA控制器设计方案。采用自适应时钟控制机制,通过加入时钟门控技术,根据DMA数据传输需求动态调整时钟,使DMA引擎模块功耗降低了62%。针对暂停需求,采用了一种可暂停的控制策略,通过加入暂停指令,实现对DMA传输的实时暂停和恢复,提高了DMA控制器的灵活性。为了保证DMA控制器功能的正确性和完备性,采用基于覆盖率驱动验证(CDV)的验证策略,划分DMA控制器的功能点,针对每个功能点编写测试用例,搭建通用验证方法学(UVM)仿真验证平台,进行大量随机测试和定向测试,给出了测试的结果以及完整的覆盖率分析结果。

基于二阶边缘检测算法的随机架构设计

数字图像边缘是具有明显亮度变化的像素集合,边缘检测是识别图像边缘的最佳方法。其中,二阶边缘检测算法具有很强的边缘定位能力,但在硬件实现上需要消耗大量资源,且易受到电路的内部噪声影响。文章提出拉普拉斯(Laplace)和高斯拉普拉斯(Laplacian of Gaussian,LoG)2种常见二阶边缘检测算法的随机电路结构,并控制输入比特流的相关性来优化电路,进一步提高运行效率。实验结果表明,相比于传统的加权二进制实现,该电路消耗更少的功耗和电路面积,同时拥有更高的容错性。

基于高密度计算的多核处理器电力芯片低功耗设计系统

多核处理器电力芯片是目前多种系统的重要组成部分,设计低功耗电力芯片,能够更好地保证系统正常运行。目前设计的电力芯片低功耗系统运行速度较慢,功耗难以达到用户要求,为此该文应用高密度计算设计了一种多核处理器电力芯片低功耗系统。兼容系统多核处理器与层次化AHB总线,探索处理器电力芯片的整体结构,集中处理存储数据信息,不断调整系统算法参数,通过高密度分析引入矩阵进行数据解析,确保运行过程的安全性。在分析处理器调度性能的基础上,利用高密度处理对数据进行层次化处理,避免数据冗余造成的系统运行故障。实验结果表明,引入所设计系统后电力芯片功耗减少了60%,加速比达到3.992,可以有效提高电力芯片运行性能。