This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important ...This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important area while designing the VLSI chip. Today almost all of the high speed switching devices include the Ternary Content Addressable Memory (TCAM) as one of the most important features. When a device consumes less power that becomes reliable and it would work with more efficiency. Complementary Metal Oxide Semiconductor (CMOS) technology is best known for low power consumption devices. This paper aims at designing a router application device which consumes less power and works more efficiently. Various strategies, methodologies and power management techniques for low power circuits and systems are discussed in this research. From this research the challenges could be developed that might be met while designing low power high performance circuit. This work aims at developing Data Aware AND-type match line architecture for TCAM. A TCAM macro of 256 × 128 was designed using Cadence Advanced Development Environment (ADE) with 90 nm technology file from Taiwan Semiconductor Manufacturing Company (TSMC). The result shows that the proposed Data Aware architecture provides around 35% speed and 45% power improvement over existing architecture.展开更多
在现代电力系统中,配网低电压问题常由多种因素引起,包括不平衡负荷、过长的供电距离或设备老化等。这些问题不仅影响电能质量,而且会降低用户满意度和电网运行效率。而智能电表的广泛部署为实时监控和管理配网提供了新的可能。文章深...在现代电力系统中,配网低电压问题常由多种因素引起,包括不平衡负荷、过长的供电距离或设备老化等。这些问题不仅影响电能质量,而且会降低用户满意度和电网运行效率。而智能电表的广泛部署为实时监控和管理配网提供了新的可能。文章深入探讨基于智能电表高速电力线载波(High-speed Power Line Carrier,HPLC)模块96点数据的配网低电压治理方法,根据自动识别和分类低电压问题,开发数据驱动的电压调节策略,并结合预测模型和预防措施,提出一套综合治理方案。然后,通过系统测试,验证所提方法的有效性和实用性。展开更多
文摘This paper represents current research in low-power Very Large Scale Integration (VLSI) domain. Nowadays low power has become more sought research topic in electronic industry. Power dissipation is the most important area while designing the VLSI chip. Today almost all of the high speed switching devices include the Ternary Content Addressable Memory (TCAM) as one of the most important features. When a device consumes less power that becomes reliable and it would work with more efficiency. Complementary Metal Oxide Semiconductor (CMOS) technology is best known for low power consumption devices. This paper aims at designing a router application device which consumes less power and works more efficiently. Various strategies, methodologies and power management techniques for low power circuits and systems are discussed in this research. From this research the challenges could be developed that might be met while designing low power high performance circuit. This work aims at developing Data Aware AND-type match line architecture for TCAM. A TCAM macro of 256 × 128 was designed using Cadence Advanced Development Environment (ADE) with 90 nm technology file from Taiwan Semiconductor Manufacturing Company (TSMC). The result shows that the proposed Data Aware architecture provides around 35% speed and 45% power improvement over existing architecture.
文摘在现代电力系统中,配网低电压问题常由多种因素引起,包括不平衡负荷、过长的供电距离或设备老化等。这些问题不仅影响电能质量,而且会降低用户满意度和电网运行效率。而智能电表的广泛部署为实时监控和管理配网提供了新的可能。文章深入探讨基于智能电表高速电力线载波(High-speed Power Line Carrier,HPLC)模块96点数据的配网低电压治理方法,根据自动识别和分类低电压问题,开发数据驱动的电压调节策略,并结合预测模型和预防措施,提出一套综合治理方案。然后,通过系统测试,验证所提方法的有效性和实用性。
