Electrical Properties of Ultra Thin Nitride/Oxynitride Stack Dielectrics pMOS Capacitor with Refractory Metal Gate

Electrical properties of high quality ultra thin nitride/oxynitride(N/O)stack dielectrics pMOS capacitor with refractory metal gate electrode are investigated,and ultra thin (<2 nm) N/O stack gate dielectrics with significant low leakage current and high resistance to boron penetration are fabricated.Experiment results show that the stack gate dielectric of nitride/oxynitride combined with improved sputtered tungsten/titanium nitride (W/TiN) gate electrode is one of the candidates for deep sub-micron metal gate CMOS devices.

Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

The decreasing feature sizes in complementary metal-oxide semiconductor （CMOS） transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant （high-k） because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability. In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology. Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties. It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling. In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices. Therefore, detailed atomic- scale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks, are highly required. In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed. Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy （HRTEM） and the related techniques based on scanning transmission electron microscopy （STEM）, including high-angle annular dark- field （HAADF） imaging （also known as Z-contrast imaging）, electron energy-loss spectroscopy （EELS）, and energy dispersive X-ray spectroscopy （EDS）, due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric gate stacks in the present and future generations of CMOS devices. In Section 1 of this review, the working principles of each technique are briefly introduced and their key features are outlined. In Section 2, microstructural characterizations of high-k gate dielectrics at atomic-scale by electron microscopy are critically reviewed by citing some recent results reported on high-k gate dielectrics. In Section 3, metal gate electrodes and the interfacial structures between high-k dielectrics and metal gates are discussed. The electron beam damage effects in high-k gate stacks are also evaluated, and their origins and prevention are described in Section 4. Finally, we end this review with personal perspectives towards the future challenges of atomic-scale material characterization in advanced CMOS gate stacks.

A novel partial silicon on insulator high voltage LDMOS with low-k dielectric buried layer

A novel partial silicon-on-insulator （PSOI） high voltage device with a low-k （relative permittivity） dielectric buried layer （LK PSOI） and its breakdown mechanism are presented and investigated by MEDICI. At a low k value the electric field strength in the dielectric buried layer （EI） is enhanced and a Si window makes the substrate share the vertical drop, resulting in a high vertical breakdown voltage; in the lateral direction, a high electric field peak is introduced at the Si window, which modulates the electric field distribution in the SOI layer; consequently, a high breakdown voltage （BV） is obtained. The values of EI and BV of LK PSOI with ki = 2 on a 2μm thick SOI layer over 1μm thick buried layer are enhanced by 74% and 19%, respectively, compared with those of the conventional PSOI. Furthermore, the Si window also alleviates the self-heating effect.

The influence and explanation of fringing-induced barrier lowering on sub-100 nm MOSFETs with high-k gate dielectrics

The fringing-induced barrier lowering（FIBL） effect of sub-100 nm MOSFETs with high-k gate dielectrics is investigated using a two-dimensional device simulator.An equivalent capacitance theory is proposed to explain the physics mechanism of the FIBL effect.The FIBL effect is enhanced and the short channel performance is degraded with increasing capacitance.Based on equivalent capacitance theory,the influences of channel length,junction depth,gate/lightly doped drain（LDD） overlap length,spacer material and spacer width on FIBL is thoroughly investigated.A stack gate dielectric is presented to suppress the FIBL effect.

Improved performance of back-gate MoS2 transistors by NH3-plasma treating high-k gate dielectrics

NH3-plasma treatment is used to improve the quality of the gate dielectric and interface. Al2O3 is adopted as a buffer layer between HfO2 and MoS2 to decrease the interface-state density. Four groups of MOS capacitors and back-gate transistors with different gate dielectrics are fabricated and their C–V and I–V characteristics are compared. It is found that the Al2O3/HfO2 back-gate transistor with NH3-plasma treatment shows the best electrical performance: high on–off current ratio of 1.53 × 107, higher field-effect mobility of 26.51 cm2/V·s, and lower subthreshold swing of 145 m V/dec.These are attributed to the improvements of the gate dielectric and interface qualities by the NH3-plasma treatment and the addition of Al2O3 as a buffer layer.

Gate Current for MOSFETs with High k Dielectric Materials

The MOSFET gate currents of high k gate dielectrics due to direct tunneling are investigated by using a new direct tunneling current model developed.The model includes both the inversion layer quantization effect with finite barrier height and the polysilicon depletion effect.The impacts of dielectric constant and conduction band offset as well as the band gap on the gate current are discussed.The results indicate that the gate dielectric materials with higher dielectric constant,larger conduction band offset and the larger band gap are necessary to reduce the gate current.The calculated results can be used as a guide to select the appropriate high k gate dielectric materials for MOSFETs.

MOS器件Hf基高k栅介质的研究综述

随着金属氧化物半导体(MOS)器件尺寸的持续缩小,HfO2因其介电常数(k)高、带隙大等特点,成为取代传统SiO2栅介质最有希望的候选材料.本文综述了Hf基高k栅介质薄膜的近年的研究进展.针对HfO2结晶温度低、在HfO2薄膜和Si衬底间易形成界面层导致漏电流大、界面态密度高、击穿电压低等问题,回顾了最近论文报道的两种策略,即掺杂改性和插入缓冲层.接着举例讨论了Hf基材料从二元到掺杂氧化物/复合物的演变、非Si衬底上淀积Hf基高k栅介质、Hf基高k栅介质的非传统MOS器件结构,为集成电路(IC)中MOS器件的长期发展提供一些思路.

Characterization of Sub-100nm MOSFETs with High K Gate Dielectric

The short-channel performance of typical 70nm MOSFETs with high K gate dielectric is widely studied by using a two dimensional(2-D) device simulator.The short-channel performance is degraded from the fringing field and lower the source/drain junction resistance.The sidewall material is found very useful to eliminate the fringing-induced berrier lowing effect.

A novel power UMOSFET with a variable K dielectric layer

A novel split-gate power UMOSFET with a variable K dielectric layer is proposed. This device shows a 36.2% reduction in the specific on=state resistance at a breakdown voltage of 115 V, as compared with the SGE-UMOS device. Numerical simulation results indicate that the proposed device features high performance with an improved figure of merit of Qg × RON and BV^2/RON, as compared with the previous power UMOSFET.

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

This paper presents a new silicon-on-insulator(SOI) lateral-double-diffused metal-oxide-semiconductor transistor(LDMOST) device with alternated high-k dielectric and step doped silicon pillars(HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage(BV) and specific on-resistance(R_(on,sp)) are obtained. The results indicate that the HKSD device has a higher BV and lower R_(on,sp) compared to the SD device and HK device.

Investigation of a 4H-SiC metal-insulationsemiconductor structure with an A1203/SiO2 stacked dielectric

Atomic layer deposited （ALD） Al2O3/dry-oxidized ultrathin SiO2 films as a high-k gate dielectric grown on 8° off-axis 4H-SiC （0001） epitaxial wafers are investigated in this paper. The metal-insulation-semiconductor （MIS） capacitors, respectively with different gate dielectric stacks （Al2O3/SiO2, Al2O3, and SiO2） are fabricated and compared with each other. The I-V measurements show that the Al2O3/SiO2 stack has a high breakdown field （≥12 MV/cm） comparable to SiO2, and a relatively low gate leakage current of 1 × 10-7 A/cm2 at an electric field of 4 MV/cm comparable to Al2O3. The 1-MHz high frequency C-V measurements exhibit that the Al2O3/SiO2 stack has a smaller positive flat-band voltage shift and hysteresis voltage, indicating a less effective charge and slow-trap density near the interface.

Effect of interface-roughness scattering on mobility degradation in SiGe p-MOSFETs with a high-k dielectric/SiO2 gate stack＊

A physical model for mobility degradation by interface-roughness scattering and Coulomb scattering is proposed for SiGe p-MOSFET with a high-k dielectric/SiO2 gate stack. Impacts of the two kinds of scatterings on mobility degradation are investigated. Effects of interlayer （SiO2） thickness and permittivities of the high-k dielectric and interlayer on carrier mobility are also discussed. It is shown that a smooth interface between high-k dielectric and interlayer, as well as moderate permittivities of high-k dielectrics, is highly desired to improve carriers mobility while keeping alow equivalent oxide thickness. Simulated results agree reasonably with experimental data.

HfO_2 Gate Dielectrics for Future Generation of CMOS Device Application

The material and electrical properties of HfO 2 hi gh-k gate dielectric are reported.In the first part,the band alignment of H fO 2 and (HfO 2) x(Al 2O 3) 1-x to (100)Si substrate and thei r thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO 2) x(Al 2O 3) 1-x,the valence band offset, and the conduction band offset between (HfO 2) x(Al 2O 3) 1-x and the Si substrate as functions of x are obtained based on the XPS results .Our XPS results also demonstrate that both the thermal stability and the resist ance to oxygen diffusion of HfO 2 are improved by adding Al to form Hf aluminat es.In the second part,a thermally stable and high quality HfN/HfO 2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage, and work function (close to Si mid-gap) of HfN/HfO 2 gate stack are demonstrat ed even after 1000℃ post-metal annealing(PMA),which is attributed to the super ior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/ HfO 2 interface.Therefore,even without surface nitridation prior to HfO 2 depo sition,the EOT of HfN/HfO 2 gate stack has been successfully scaled down to les s than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.T he last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO 2 gate dielectric.The excellent thermal stability of the HfN/HfO 2 gate stack enables its use in high temperature CMOS processes.Th e replacement of HfN with other metal gate materials with work functions adequat e for n- and p-MOS is facilitated by a high etch selectivity of HfN with respe ct to HfO 2,without any degradation to the EOT,gate leakage,or TDDB characteris tics of HfO 2.

Current Progress of Hf(Zr)-Based High-k Gate Dielectric Thin Films

With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant （high-k） gate materials, as alternatives to SiO2, have been extensively investigated. Hf （Zr）-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf （Zr）-based high-k gate dielectrics based on PVD （physical vapor deposition） process. This article begins with a survey of various methods developed for generating Hf （Zr）-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf （Zr）-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf （Zr）-based high-k gate dielectrics.

4H-SiC基功率器件的high-k栅介质材料研究进展

金属氧化物半导体场效应晶体管(MOSFET)作为碳化硅绝缘栅结构的典型器件被广泛使用,然而SiO_(2)介电常数低的缺点和SiO_(2)/4H-SiC界面特性差的问题一直制约着4H-SiC绝缘栅结构(金属-绝缘体-半导体,MIS)器件更大规模商业化应用,因此科研工作者一直致力于寻找能够替代或弥补SiO_(2)的high-k栅介质材料。本文对该科学问题的研究现状进行综述,首先指出合适的high-k栅介质材料应该拥有较宽的禁带宽度、较高的介电常数、良好的界面特性和热稳定性。然后,主要从栅薄膜制备工艺、沉积温度、栅介质界面特性和电学性能等方面对典型high-k栅介质材料的研究结果进行评价,包括氧化铪(HfO_(2))、氧化铝(Al_(2)O_(3))、氮化铝(AlN)、氧化钇(Y_(2)O_(3))、氧化铈(CeO_(2))、氧化锆(ZrO_(2))、氧化镧(La_(2)O_(3))、五氧化二钽(Ta_(2)O_(5))、钛酸钡(BaTiO_(3))、氧化钬(Ho_(2)O_(3))和由它们组合而成的堆栈栅介质。最后,对未来该领域的研究方向进行了展望和建议,例如对栅漏电流机理的研究、对新材料的更多尝试、器件在极端环境下的可靠性问题等。

Energy-band alignment of atomic layer deposited(HfO_2)_x(Al_2O_3)_(1-x) gate dielectrics on 4H-SiC

We study a series of（HfO2）x（Al2O3）1-x /4H-SiC MOS capacitors. It is shown that the conduction band offset of HfO2 is 0.5 e V and the conduction band offset of Hf AlO is 1.11–1.72 e V. The conduction band offsets of（Hf O2）x（Al2O3）1-x are increased with the increase of the Al composition, and the（HfO2）x（Al2O3）1-x offer acceptable barrier heights（〉 1 e V）for both electrons and holes. With a higher conduction band offset,（Hf O2）x（Al2O3）1-x/4H-SiC MOS capacitors result in a ～ 3 orders of magnitude lower gate leakage current at an effective electric field of 15 MV/cm and roughly the same effective breakdown field of ～ 25 MV/cm compared to HfO2. Considering the tradeoff among the band gap, the band offset, and the dielectric constant, we conclude that the optimum Al2O3 concentration is about 30% for an alternative gate dielectric in 4H-Si C power MOS-based transistors.

Designing high k dielectric films with LiPON-Al_(2)O_(3)hybrid structure by atomic layer deposition

A large amount of ultra-low-power consumption electronic devices are urgently needed in the new era of the internet of things,which demand relatively low frequency response.Here,atomic layer deposition has been utilized to fabricate the ion polarization dielectric of the Li PON-Al_(2)O_(3) hybrid structure.The Li PON thin film is periodically stacked in the Al_(2)O_(3) matrix.This hybrid structure presents a frequency-dependent dielectric constant,of which k is significantly higher than the aluminum oxide matrix from 1 k Hz to 200 k Hz in frequency.The increased dielectric constant is attributed to the lithium ions shifting locally upon the applied electrical field,which shows an additional polarization to the Al_(2)O_(3) matrix.This work provides a new strategy with promising potential to engineers for the dielectric constant of the gate oxide and sheds light on the application of electrolyte/dielectric hybrid structure in a variety of devices from capacitors to transistors.

Effect of F doping on capacitance-voltage characteristics of SiCOH low-k films metal-insulator-semiconductor

This paper investigates the capacitance-voltage （C-V） characteristics of F doping SiCOH low dielectric constant films metal-insulator-semiconductor structure. The F doping SiCOH films are deposited by decamethylcyclopentasilox-ane [DMCPS） and trifluromethane （CHF3） electron cyclotron resonance plasmas. With the CHF3/DMCPS flow rate ratio from 0 to 0.52, the positive excursion of C-V curves and the increase of fiat-band voltage VFB from -6.1 V to 32.2V are obtained. The excursion of C-V curves and the shift of VFB are related to the change of defects density and type at the Si/SiCOH interface due to the decrease of Si and O concentrations, and the increase of F concentration. At the CHF3/DMCPS flow rate ratio is 0.12, the compensation of F-bonding dangling bond to Si dangling bond leads to a small VFB of 2.0V.

U型高K介质膜槽栅垂直场板LDMOS

近年来,随着汽车电子和电源驱动的发展,集成度较高的LDMOS作为热门功率器件受到了关注,如何提高其击穿电压与降低其比导通电阻成为提高器件性能的关键。基于SOI LDMOS技术,文章提出了在被4μm的高K介质膜包围的SiO_(2)沟槽中引入垂直场板的新型结构。与传统沟槽LDMOS相比,垂直场板和高K介质膜充分地将电势线引导至沟槽中,提高了击穿电压。此外垂直场板与高K介质和漂移区形成的MIS金属-绝缘层-半导体电容结构能增加漂移区表面的电荷量,降低比导通电阻。通过二维仿真软件,在7.5μm深的沟槽中引入宽0.3μm、深6.8μm的垂直场板,实现了具有300 V的击穿电压和4.26 mΩ·cm^(2)的比导通电阻,以及21.14 MW·cm^(-2)的Baliga品质因数的LDMOS器件。

A threshold voltage analytical model for high-k gate dielectric MOSFETs with fully overlapped lightly doped drain structures

We investigate the influence of voltage drop across the lightly doped drain（LDD） region and the built-in potential on MOSFETs,and develop a threshold voltage model for high-k gate dielectric MOSFETs with fully overlapped LDD structures by solving the two-dimensional Poisson＇s equation in the silicon and gate dielectric layers.The model can predict the fringing-induced barrier lowering effect and the short channel effect.It is also valid for non-LDD MOSFETs.Based on this model,the relationship between threshold voltage roll-off and three parameters,channel length,drain voltage and gate dielectric permittivity,is investigated.Compared with the non-LDD MOSFET,the LDD MOSFET depends slightly on channel length,drain voltage,and gate dielectric permittivity.The model is verified at the end of the paper.