In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loo...In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.展开更多
A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stabili...A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stability is achieved without an off-chip capacitor. The chip was implemented in CSMC＇s 0.5μm CMOS technology and the die area is 600μm×480μm. The error of the output voltage due to line variation is less than -＋ 0.21% ,and the quiescent current is 39.8μA. The power supply rejection ratio at 100kHz is -33.9dB, and the output noise spectral densities at 100Hz and 100kHz are 1.65 and 0.89μV √Hz, respectively.展开更多
A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins ...A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.展开更多
An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage ...An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.展开更多
为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出...为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出电压经反馈网络传递给反馈端的信号耦合形成由负载电容、负载电流控制的可控零点,可有效提高LDO电路整体的稳定性。此外,电路内部加入了产生动态极点的自适应电流补偿电路以保证次极点不会对环路的相位裕度产生影响。基于0.18μm BCD工艺设计,该电路在0~800 mA的宽负载范围、5 V输入3.3 V输出下相位裕度均高于48°,适用负载电容范围≥1μF,同时该LDO在10~100 kHz的频率范围内输出噪声仅为5.0617μVrms。展开更多
A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique...A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm^2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.展开更多
This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, whic...This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 x 550 μm^2 and the quiescent current is 130 μA.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62274189the Natural Science Foundation of Guangdong Province,China,under Grant 2022A1515011054the Key Area R&D Program of Guangdong Province under Grant 2022B0701180001.
文摘In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.
文摘A stable CMOS low drop-out regulator without an off-chip capacitor for system-on-chip application is presen- ted. By using an on-chip pole splitting technique and an on-chip pole-zero canceling technique, high stability is achieved without an off-chip capacitor. The chip was implemented in CSMC＇s 0.5μm CMOS technology and the die area is 600μm×480μm. The error of the output voltage due to line variation is less than -＋ 0.21% ,and the quiescent current is 39.8μA. The power supply rejection ratio at 100kHz is -33.9dB, and the output noise spectral densities at 100Hz and 100kHz are 1.65 and 0.89μV √Hz, respectively.
基金The Key Science and Technology Project of Zhejiang Province(No.2007C21021)
文摘A CMOS （complementary metal-oxide-semiconductor transistor） low-dropout regulator （LDO） with 3. 3 V output voltage and 100 mA output current for system-on-chip applications to reduce board space and external pins is presented. By utilizing a dynamic slew-rate enhancement（SRE） circuit and nested Miller compensation （NMC） on the LDO structure, the proposed LDO provides high stability during line and load regulation without off-chip load capacitors. The overshot voltage is limited within 550 mV and the settling time is less than 50 μs when the load current decreases from 100 mA to 1 mA. By using a 30 nA reference current, the quiescent current is 3.3 μA. The proposed design is implemented by CSMC 0. 5 μm mixed-signal process. The experimental results agree with the simulation results.
文摘An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.
基金Project supported by the National Natural Science Foundation of China(No60876023)
文摘A 3 A sink/source G_m-driven CMOS low-dropout regulator（LDO）,specially designed for low input voltage and low cost,is presented by utilizing the structure of a current mirror G_m（transconductance）driving technique,which provides high stability as well as a fast load transient response.The proposed LDO was fabricated by a 0.5μm standard CMOS process,and the die size is as small as 1.0 mm^2.The proposed LDO dissipates 220μA of quiescent current in no-load conditions and is able to deliver up to 3 A of load current.The measured results show that the output voltage can be resumed within 2μs with a less than 1mV overshoot and undershoot in the output current step from-1.8 to 1.8 A with a 0.1μs rising and falling time at three 10μF ceramic capacitors.
文摘This paper presents a 200 mA low-dropout （LDO） linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8-5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 x 550 μm^2 and the quiescent current is 130 μA.
