In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loo...In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.展开更多
为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出...为提高低压差线性稳压器(Low-DropOut Linear Regulator,LDO)的稳定性并降低前馈电路所产生的噪声,提出了一种生成自适应补偿零点的低噪声前馈电路。该前馈电路通过镜像调整管的负载电流,通过低值反馈电阻形成高增益反馈信号,与LDO输出电压经反馈网络传递给反馈端的信号耦合形成由负载电容、负载电流控制的可控零点,可有效提高LDO电路整体的稳定性。此外,电路内部加入了产生动态极点的自适应电流补偿电路以保证次极点不会对环路的相位裕度产生影响。基于0.18μm BCD工艺设计,该电路在0~800 mA的宽负载范围、5 V输入3.3 V输出下相位裕度均高于48°,适用负载电容范围≥1μF,同时该LDO在10~100 kHz的频率范围内输出噪声仅为5.0617μVrms。展开更多
An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage ...An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.展开更多
A low-dropout voltage regulator,LM2941,was irradiated by ^(60)Coγ-rays at various dose rates and biases for investigating the total dose and dose rate effects.The radiation responses show that the key electrical para...A low-dropout voltage regulator,LM2941,was irradiated by ^(60)Coγ-rays at various dose rates and biases for investigating the total dose and dose rate effects.The radiation responses show that the key electrical parameters, including its output and dropout voltage,and the maximum output current,are sensitive to total dose and dose rates, and are significantly degraded at low dose rate and zero bias.The integrated circuits damage change with the dose rates and biases,and the dose-rate effects are relative to its electric field.展开更多
This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMO...This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMOS Process.It can guarantee 150mA output current per circuit and the leakage voltage is 60mV,1nA quiescent current when both are in shutdown mode,and it has 115μA ground current,output noise is 42μVrms,130μs fast turn-on circuitry and the junction temperature range is-40℃to 125℃.展开更多
Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout ...Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.展开更多
基金supported by the National Natural Science Foundation of China under Grant 62274189the Natural Science Foundation of Guangdong Province,China,under Grant 2022A1515011054the Key Area R&D Program of Guangdong Province under Grant 2022B0701180001.
文摘In this paper,an NMOS output-capacitorless low-dropout regulator(OCL-LDO)featuring dual-loop regulation has been proposed,achieving fast transient response with low power consumption.An event-driven charge pump(CP)loop with the dynamic strength control(DSC),is proposed in this paper,which overcomes trade-offs inherent in conventional structures.The presented design addresses and resolves the large signal stability issue,which has been previously overlooked in the event-driven charge pump structure.This breakthrough allows for the full exploitation of the charge-pump structure's poten-tial,particularly in enhancing transient recovery.Moreover,a dynamic error amplifier is utilized to attain precise regulation of the steady-state output voltage,leading to favorable static characteristics.A prototype chip has been fabricated in 65 nm CMOS technology.The measurement results show that the proposed OCL-LDO achieves a 410 nA low quiescent current(IQ)and can recover within 30 ns under 200 mA/10 ns loading change.
文摘An ultra-low quiescent current low-dropout regulator with small output voltage variations and improved load regulation is presented in this paper. It makes use of dynamically-biased shunt feedback as the buffer stage and the LDO regulator can be stable for all load conditions. The proposed structure also employs a momentarily current-boosting circuit to reduce the output voltage to the normal value when output is switched from full load to no load. The whole circuit is designed in a 0.18 μm CMOS technology with a quiescent current of 550 nA. The maximum output voltage variation is less than 20 mV when used with 1 μF external capacitor.
文摘A low-dropout voltage regulator,LM2941,was irradiated by ^(60)Coγ-rays at various dose rates and biases for investigating the total dose and dose rate effects.The radiation responses show that the key electrical parameters, including its output and dropout voltage,and the maximum output current,are sensitive to total dose and dose rates, and are significantly degraded at low dose rate and zero bias.The integrated circuits damage change with the dose rates and biases,and the dose-rate effects are relative to its electric field.
基金This work was supported by Supported by the 2016 Annual Young Academic Leaders Scientific Research Foundation of Chengdu University of Information Technology(No.J201604)and the National Social Science Foundation(No.61504014).
文摘This paper presents a dual micro-power 150mA ultra LDO CMOS regulator,which is designed for high performance and small size portable wireless devices.The proposed LDO has been designed and simulated in 0.5μm 2P3M CMOS Process.It can guarantee 150mA output current per circuit and the leakage voltage is 60mV,1nA quiescent current when both are in shutdown mode,and it has 115μA ground current,output noise is 42μVrms,130μs fast turn-on circuitry and the junction temperature range is-40℃to 125℃.
基金supported by the National Natural Science Foundation of China(No.61974046)the Provincial Key Research and Development Program of Guangdong(2019B010140002)the Macao Science&Technology Development Fund(FDCT)145/2019/A3 and SKL-AMSV(UM)-2020-2022.
文摘Granular power management in a power-efficient system on a chip(SoC)requires multiple integrated voltage regulators with a small area,process scalability,and low supply voltage.Conventional on-chip analog low-dropout regulators(ALDOs)can hardly meet these requirements,while digital LDOs(DLDOs)are good alternatives.However,the conventional DLDO,with synchronous control,has inherently slow transient response limited by the power-speed trade-off.Meanwhile,it has a poor power supply rejection(PSR),because the fully turned-on power switches in DLDO are vulnerable to power supply ripples.In this comparative study on DLDOs,first,we compare the pros and cons between ALDO and DLDO in general.Then,we summarize the recent DLDO advanced techniques for fast transient response and PSR enhancement.Finally,we discuss the design trends and possible directions of DLDO.
