Design of Low-Power Data Logger of Deep Sea for Long-Term Field Observation

This paper describes the implementation of a data logger for the real-time in-situ monitoring of hydrothermal systems. A compact mechanical structure ensures the security and reliability of data logger when used under deep sea. The data logger is a battery powered instrument, which can connect chemical sensors （pH electrode, H2S electrode, H2 electrode） and temperature sensors. In order to achieve major energy savings, dynamic power management is implemented in hardware design and software design. The working current of the data logger in idle mode and active mode is 15 μA and 1.44 mA respectively, which greatly extends the working time of battery. The data logger has been successftdly tested in the first Sino-American Cooperative Deep Submergence Project from August 13 to September 3, 2005.

LOW-FREQUENCY LOW-NOISE CIRCUITS DESIGN USING AN E_n-I_n MODEL

In view of the limitations of a Rn-Gn model in the low frequency range and the defects of an En-In model in common use now, this paper builds a complete En-In model according to the theory of random harmonic. The parameters for the low-noise design such as the equivalent input noisy voltage Ens, the optimum source impedance Zsopt and the minimum noise figure Fmin can be calculated accurately by using this En-In model because it considers the coherence between the noise sources fully. Moreover, this paper points out that it will cause the maximum 30% miscalculation when neglecting the effects of the correlation coefficient 7. Using the series-series circuits as an example, this paper discusses the methods for the En-In noise analysis of electronic circuits preliminarily and demonstrates its correctness through the comparison between the simulated and measured results of the minimum noise figure Fmin of a single current series negative feedback circuit.

A low-power Bluetooth-based wireless sensor network and its global confliction-solving impact localization method

During the whole service lifetime of aircraft structures with composite materials,impacts are inevitable and can usually cause severe but barely visible damages.Since the occurrences of impact are random and unpredictable,it is a hotspot direction to develop an online impact monitoring system that can meet strict limitations of aerospace applications including small size,light weight,and low power consumption.Piezoelectric(PZT)sensor,being able to generate impact response signals with no external power and cover a large-scale structure with only a small amount of them,is a promising choice.Meanwhile,for real systems,networks with multiple nodes are normally required to monitor large-scale structures in a global way to identify any impact localization confliction,yet the existing studies are mostly evaluated with single nodes instead of networks.Therefore,in this paper,based on a new low-power node designed,a Bluetooth-based digital impact monitoring PZT sensor network is proposed for the first time with its global confliction-solving impact localization method.Evaluations of the system as a network are researched and analyzed on a complex real aircraft wing box for a global confliction-solving impact localization,showing a satisfying high accuracy.

Design of Wireless Multi-media Sensor Network for Precision Agriculture

To satisfy the needs of modem pre-cision agriculture, a Precision Agriculture Sensing System （PASS） is designed, which is based on wireless multimedia sensor network. Both hardware and software of PASS are tai-lored for sensing in wide farmland without human supervision. A dedicated single-chip sensor node platform is designed specially for wireless multi-media sensor network. To guarantee the bulky data transmission, a bit-map index reliable data transmission mecha-nism is proposed. And a battery-array switch-ing system is design to power the sensor node to elongate the lifetime. The effectiveness and performance of PASS have been evaluated through comprehensive experiments and large-scale real-life deployment.

MOSFET-like CNFET based logic gate library for low-power application:a comparative study

The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.

Reducing Power and Energy Consumption of Nonvolatile Microcontrollers with Transparent On-Chip Instruction Cache

Demands for low-energy microcontrollers have been increasing in recent years. Since most microcontrollers achieve user programmability by integrating nonvolatile (NV) memories such as flash memories for storing their programs, the large power consumption required in accessing an NV memory has become a major problem. This problem becomes critical when the power supply voltage of NV microcontrollers is decreased. We can solve this problem by introducing an instruction cache, thus reducing the access frequency of the NV memory. Unlike general-purpose microprocessors, microcontrollers used for real-time applications in embedded systems must accurately calculate program execution time prior to its execution. Therefore, we introduce a “transparent” instruction cache, which does not change the existing NV microcontroller’s cycle-level execution time, for reducing power and energy consumption, but not for improving the processing speed. We have conducted detailed microar chitecture design based on the architecture of a major industrial microcontroller, and we evaluated power and energy consumption for several benchmark programs. Our evaluation shows that the proposed instruction cache can successfully reduce energy consumption in a fairly wide range of practical NV microcontroller configurations.

Design of an analog front-end for ambulatory biopotential measurement systems

A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms （0.48-2000 Hz）. The chip is fabricated via a SMIC 0.18μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.

Toward the Optimal Configuration of Dynamic Voltage Scaling Points in Real-Time Applications

In real-time applications, compiler-directed dynamic voltage scaling （DVS） could reduce energy consumption efficiently, where compiler put voltage scaling points in the proper places, and the supply voltage and clock frequency were adjusted to the relationship between the reduced time and the reduced workload. This paper presents the optimal configuration of dynamic voltage scaling points without voltage scaling overhead, which minimizes energy consumption. The conclusion is proved theoretically. Finally, it is confirmed by simulations with equally-spaced voltage scaling configuration.

The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy

This paper explores potential for the RAMpage memory hierarchy to use a microkernel with a small memory footprint, in a specialized cache-speed static RAM （tightly-coupled memory, TCM）. Dreamy memory is DRAM kept in low-power mode, unless referenced. Simulations show that a small microkernel suits RAMpage well, in that it achieves significantly better speed and energy gains than a standard hierarchy from adding TCM. RAMpage, in its best 128KB L2 case, gained 11% speed using TCM, and reduced energy 14%. Equivalent conventional hierarchy gains were under 1%. While 1MB L2 was significantly faster against lower-energy cases for the smaller L2, the larger SRAM＇s energy does not justify the speed gain. Using a 128KB L2 cache in a conventional architecture resulted in a best-case overall run time of 2.58s, compared with the best dreamy mode run time （RAMpage without context switches on misses） of 3.34s, a speed penalty of 29%. Energy in the fastest 128KB L2 case was 2.18J vs. 1.50J, a reduction of 31%. The same RAMpage configuration without dreamy mode took 2.83s as simulated, and used 2.393, an acceptable trade-off （penalty under 10%） for being able to switch easily to a lower-energy mode.