Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swi...Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor （CMOS） interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.展开更多
A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage l...A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.展开更多
a low-power register file is designed by using a low-swing strategy and modified NAND address decoders. The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedb...a low-power register file is designed by using a low-swing strategy and modified NAND address decoders. The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedback power.This method contains two parts：WRITE and READ strategy.In the WRITE low-swing scheme,the modified memory cell is used to support low-swing WRITE.The modified NAND decoder not only dissipates less power,but also enables a great deal of area reduction.Compared with the conventional single-ended register file,the low-swing strategy saves 34.5%and 51.15%bit-line power in WRITE and READ separately.The post simulation results indicate a 39.4%power improvement when the twelve ports are all busy.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066)the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260)the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005)
文摘Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing arid adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-am and 90-nm complementary metal-oxide semiconductor （CMOS） interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.
基金the 973 Program of China (Grant No.G1999032903)the National Science Fund for Distinguished Young Scholars (Grant No.60025101)the Major Program of National Natural Science Foundation of China (Grant No.90707002)
文摘A novel low-swing interface circuit for high-speed on-chip asynchronous interconnection is proposed in this paper. It takes a differential level-triggered latch to recover digital signal with ultra low-swing voltage less than 50 mV, and the driver part of the interface circuit is optimized for low power using the driver-array method, With a capacity to work up to 500 MHz, the proposed circuit, which is simulated and fabricated using SMIC 0.18-pm 1.8-V digital CMOS technology, consumes less power than previously reported designs.
基金Proiect supported by the National Science and Technology Maior Proiects of China(No.2009ZX01034-001-002-005)
文摘a low-power register file is designed by using a low-swing strategy and modified NAND address decoders. The proposed low-swing strategy is based on the feedback scheme and uses dynamic logic to reduce the active feedback power.This method contains two parts：WRITE and READ strategy.In the WRITE low-swing scheme,the modified memory cell is used to support low-swing WRITE.The modified NAND decoder not only dissipates less power,but also enables a great deal of area reduction.Compared with the conventional single-ended register file,the low-swing strategy saves 34.5%and 51.15%bit-line power in WRITE and READ separately.The post simulation results indicate a 39.4%power improvement when the twelve ports are all busy.
