A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the c...Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.展开更多
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
基金supported by the Important National S&T Special Project of China under Grant No.2011ZX01034-002-001-2
文摘Digital circuits operating in the sub-threshold regime consume the least energy. The strict energy constraints are desired in the applications which work at the lowest possible supply voltage. On the other hand, the conventional design flow utilizes the technology library provided by the foundry with a fixed voltage boundary, which causes problems when the supply scales down to the sub-threshold regime. In this paper, we present a design methodology to characterize the existing cell library with Liberty NCX to facilitate the standard design flow. It is demonstrated in 0.13 μm complementary metal-oxide-semiconductor （CMOS） technology with the supply voltage of 300 mV.
