A complex programmable logical device （CPLD） based on conventional embedded Flash memory process with 72 macro cells is studied in the paper. Compared with the Flash cell array technology employed by foreign compani...A complex programmable logical device （CPLD） based on conventional embedded Flash memory process with 72 macro cells is studied in the paper. Compared with the Flash cell array technology employed by foreign companies, this architecture exhibiting insystem reconfiguration and rapid response was manufactured by low cost fabrication process. The device architecture and critical cell design are also analyzed in detail in the paper. The CPLD was designed by full-custom ASIC technology and manufactured by 0.35 pm 3P3M Flash process with 72 macro cells and 5 V voltage supply. The measurement results indicate that the devices are able to operate above the frequency of 66.7 MHz with the pin delay less than 10 ns.展开更多
文摘A complex programmable logical device （CPLD） based on conventional embedded Flash memory process with 72 macro cells is studied in the paper. Compared with the Flash cell array technology employed by foreign companies, this architecture exhibiting insystem reconfiguration and rapid response was manufactured by low cost fabrication process. The device architecture and critical cell design are also analyzed in detail in the paper. The CPLD was designed by full-custom ASIC technology and manufactured by 0.35 pm 3P3M Flash process with 72 macro cells and 5 V voltage supply. The measurement results indicate that the devices are able to operate above the frequency of 66.7 MHz with the pin delay less than 10 ns.
