An adaptive Mealy machine model for monitoring crop status

Variation in phenological stage is the major nonlinearity in monitoring, modeling and various estimations of agricultural systems. Indices are used as a common means of evaluating agricultural monitoring data from remote sensing and terrestrial observation systems, and many of these indices have linear characteristics. The analysis of and relationships between indices are dependent on the type of plant, but they are also highly variable with respect to its phenologicat stage. For this reason, variations in the phenologica! stage affect the performance of spatiotemporal crop status monitoring. We hereby propose an adaptive event-triggered model for monitoring crop status based on remote sensing data and terrestrial observations. In the proposed model, the estimation of phenological stage is a part of predicting crop status, and spatially distributed remote sensing parameters and temporal terrestrial monitoring data are used together as inputs in a state space system model. The temporal data are segmented with respect to the phenological stage-oriented timing of the spatial data, so instead of a generalized discrete state space model, we used logical states combined with analog inputs and adaptive trigger functions, as in the case of a Mealy machine model. This provides the necessary nonlinearity for the state transi- tions. The results showed that observation parameters have considerably greater significance in crop status monitoring with respect to conventional agricultural data fusion techniques.

FPGA-Based High-Frequency Digital Pulse Width Modulator Architecture for DC-DC Converters

Digital pulse width modulator is an integral part in digitally controlled Direct Current to Direct Current (DC-DC) converter utilized in modern portable devices. This paper presents a new Digital Pulse Width Modulator (DPWM) architecture for DC-DC converter using mealy finite state machine with gray code encoding scheme and one hot encoding method to derive the variable duty cycle Pulse Width Modulation (PWM) signal without varying the clock frequency. To verify the proposed DPWM technique, the architecture with control input of six, five and four bits are implemented and the maximum operating frequency along with power consumption results is obtained for different Field Programmable Gate Array (FPGA) devices. The post layout timing results are presented showing that architecture can work with maximum frequency of 326 MHz and derive PWM signal of 3.59 MHz. Experimental results show the implementation of the proposed architecture in low-cost FPGA (Spartan 3A) with on-board oscillator clock frequency of 12 MHz which is multiplied internally by two with Digital Clock Manager (DCM) and derive the PWM signal of 1.5 MHz with a time resolution of 1 ps.