Memory characteristics of microcavity dielectric barrier discharge

The nonlinear resistance characteristics of microcavity dielectric barrier discharge are mainly studied in the paper. A simulation model of microcavity dielectric barrier discharge is herein built to study the relationship between voltage and current in the process of discharge, and thus its I–V characteristic curve can be obtained. The I–V characteristics of the memristor are analyzed and compared with the I–V characteristics of the dielectric barrier discharge; it can be found that the I–V characteristics of the microcavity dielectric barrier discharge are similar to the characteristics of the memristor by analyzing them. The memory characteristics of microcavity dielectric barrier discharge are further analyzed.

Martensite Aging Effect and Thermal Cyclic Characteristics in Ti-Pd and Ti-Pd-Ni High Temperature Shape Memory Alloys

The effect of thermal cycling and aging in martensitic state in Ti-Pd-Ni alloys were investigated by DSC and TEM observations. It is shown that the thermal cycling causes the decreases in M, and Af temperatures in Ti50Pd50-xNix (x=10, 20, 30) alloys, but no obvious thermal cycling effect was observed in Ti50Pd50Pd40Ni10 alloys and the aging effect shows a curious feature, i.e., the Af temperature does not saturate even after relatively long time aging, which is considered to be due to the occurrence of recovery recrystallization during aging.

Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates

A novel high-κ~ A1203/HfO2/AI203 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ~4 V, a small leakage current density of ~2 ×10-6 Acre-2 at a gate voltage of 7V, a high charge trapping density of 1.42 × 1013 cm-2 at a working vo]tage of 4-10 V and good retention characteristics are observed. Furthermore, the programming （△ VFB = 2.8 V at 10 V for 10μs） and erasing speeds （△VFB =-1.7 V at -10 V for 10μs） of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.

Fabrication and Characteristics of Nano-Floating Gate Memories with ZnO Nano-Crystals as Charge-Storage Layer

Nano-floating gate memory devices with ZnO nano-crystals as charge storage layers are fabricated,and the influence of post-deposition annealing temperature and thickness of the ZnO layer are investigated.Atomic force microscopy and scanning electron microscopy reveal the morphology of discrete ZnO nano-crystals.For capacitance-voltage measurements,it is found that the memory device with 1.5 nm ZnO and annealed at 700℃shows a larger memory window of 4.3 V（at±6 V）and better retention characteristics than memoriy devices with2.5 nm ZnO or annealed at other temperatures.These results indicate that the nano-floating gate memory with ZnO nano-crystals can obtain good trade-off memory properties.

Effects of Film Thickness and Ar/O2 Ratio on Resistive Switching Characteristics of HfOx-Based Resistive-Switching Random Access Memories

Cu/HfOx/n^＋Si devices are fabricated to investigate the influence of technological parameters including film thickness and Ar/02 ratio on the resistive switching （RS） characteristics of HfOx films, in terms of switch ratio, endurance properties, retention time and multilevel storage. It is revealed that the RS characteristics show strong dependence on technological parameters mainly by altering the defects （oxygen vacancies） in the film. The sample with thickness of 2Onto and Ar/O2 ratio of 12：3 exhibits the best RS behavior with the potential of multilevel storage. The conduction mechanism of all the films is interpreted based on the filamentary model.

Improved memory performance of metal–oxide–nitride–oxide–silicon by annealing the SiO_2 tunnel layer in different nitridation atmospheres

： Metal-oxide-nitride-oxide-silicon （MONOS） capacitors with thermally grown SiO2 as the tunnel layer are fabricated, and the effects of different ambient nitridation （NH3, NO and N20） on the characteristics of the memory capacitors are investigated. The experimental results indicate that the device with tunnel oxide annealed in NO ambient exhibits excellent memory characteristics, i.e. a large memory window, high program/erase speed, and good endurance and retention performance （the charge loss rate is 14.5% after l0 years）. The mechanism involved is that much more nitrogen is incorporated into the tunnel oxide during NO annealing, resulting in a lower tunneling barrier height and smaller interface state density. Thus, there is a higher tunneling rate under a high electric field and a lower probability of trap-assisted tunneling during retention, as compared to N20 annealing. Furthermore, compared with the NH3-annealed device, no weak Si-H bonds and electron traps related to the hydrogen are introduced for the NO-annealed devices, giving a high-quality and high-reliability SiON tunneling layer and SiON/Si interface due to the suitable nitridation and oxidation roles of NO. Key words： MONOS memory; memory characteristics; annealing; nitridation