High Performance SAR ADC with Mismatch Correction Latch and Improved Comparator Clock

We propose a high performance 10-bit 100-MS/s(million samples per second)successive approximation register(SAR)analog-to-digital converter(ADC)with mismatch correction latch and improved comparator clock.Using a high-low supply voltage technology,the bias output impedance of the preamplifier of the comparator is increased.Therefore,the common mode rejection ratio(CMRR)of the comparator is improved,and further diminishing the signal-dependent offset caused by the input common-mode voltage variation.A digital-to-analog converter(DAC)control signal correction latch is proposed to correct the control signal error resulted from process mismatch.The 30-point Monte Carlo mismatch simulated results demonstrate that the minimum spurious-free dynamic range(SFDR)of the ADC is improved by 2 dB with this correction latch.To ensure sufficient high bit switching time of the DAC and sufficient low bit comparison time of the comparator,a data selector used in the comparator clock is presented.The optimized time distribution improves the performance of the SAR ADC.This prototype was fabricated using a one-poly-eight-metal(1 P8 M)55 nm complementary metal oxide semiconductor(CMOS)technology.With measured results at 1.3 V/1.5 V supply and 100-MS/s,the ADC achieves a signalto-noise and distortion ratio(SNDR)of 59.4 dB and consumes 2.1 mW,resulting in a figure of merit(FOM)of31 fJ/conversion-step.In addition,the active area of the ADC is 0.018 8 mm2.

Design of a 20-Gsps 12-bit time-interleaved analog-to-digital conversion system

The time-interleaved analog-to-digital conversion(TIADC)technique is an effective method for increasing the sampling rate in a waveform digitization system.In this study,a 20-Gsps TIADC system was designed.A wide-bandwidth performance was achieved by optimizing the analog circuits,and a sufficient effective number of bits(ENOB)performance guaranteed using the perfect reconstruction algorithm for mismatch error correction.The proposed system was verified by tests,and the results indicated that a-3 dB bandwidth of 6 GHz and the ENOB performance of 8.7 bits at 1 GHz and 7.6 bits at6 GHz were successfully achieved.

Digital Self-Calibration Technique Based on 14-Bit SAR ADC

An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.