Analogue and Mixed-Signal Production Test Speed-Up by Means of Fault List Compression

Accurate test effectiveness estimation for analogue and mixed-signal Systems on a Chip (SoCs) is currently prohibitive in the design environment. One of the factors that sky rockets fault simulation costs is the number of structural faults which need to be simulated at circuit-level. The purpose of this paper is to propose a novel fault list compression technique by defining a stratified fault list, build with a set of “representative” faults, one per stratum. Criteria to partition the fault list in strata, and to identify representative faults are presented and discussed. A fault representativeness metric is proposed, based on an error probability. The proposed methodology allows different tradeoffs between fault list compression and fault representation accuracy. These tradeoffs may be optimized for each test preparation phase. The fault representativeness vs. fault list compression tradeoff is evaluated with an industrial case study—a DC-DC (switched buck converter). Although the methodology is presented in this paper using a very simple fault model, it may be easily extended to be used with more elaborate fault models. The proposed technique is a significant contribution to make mixed-signal fault simulation cost-effective as part of the production test preparation.

Design and implementation of a reconfigurable mixed-signal SoC based on field programmable analog arrays

This work presents a reconfigurable mixed-signal system-on-chip（SoC）, which integrates switched-capacitor-based field programmable analog arrays（FPAA）, analog-to-digital converter（ADC）, digital-to-analog converter, digital down converter, digital up converter, 32-bit reduced instruction-set computer central processing unit（CPU） and other digital IPs on a single chip with 0.18 μm CMOS technology. The FPAA intellectual property could be reconfigured as different function circuits, such as gain amplifier, divider, sine generator, and so on. This single-chip integrated mixed-signal system is a complete modern signal processing system, occupying a die area of 7 × 8 mm^2 and consuming 719 mW with a clock frequency of 150 MHz for CPU and 200 MHz for ADC/DAC. This SoC chip can help customers to shorten design cycles, save board area, reduce the system power consumption and depress the system integration risk, which would afford a big prospect of application for wireless communication.

Top-Down Design of 260k Color TFT-LCD One-Chip Driver ICs

A top-down design methodology is proposed for the design of TFT-LCD one-chip driver ICs,and a 260k color, 176RGB× 220-dot TFT-LCD one-chip driver IC is successfully developed with silicon verification. This IC is a typical mixed-signal VLSI and is implemented by a 0.18μm HV CMOS process. The static power dissipation is about 5mW for 260k color display mode,and the settling time of the output grayscale voltages within 0.2% error is less than 26μs.

A 1-GHz Charge Pump PLL Frequency Synthesizer for IEEE 1394b PHY

The design procedure of an 1-GHz phase-locked loop （PLL）-based frequency synthesizer used in IEEE 1394b physical （PHY） system is presented in this paper. The PLL＇s loop dynamics are analyzed in depth and theoretical relationships between all loop parameters are clearly described. All the parameters are derived and verified by Verilog-A model, which ensures the accuracy and efficiency of the circuit design and simulation. A 4-stage ring oscillator is employed to generate 1-GHz oscillation frequency and is divided into low frequency clocks by a feedback divider. The architecture is a third-order, type-2 charge pump PLL. The simulated settling time is less than 4μs. The RMS value of period jitter of the PLL＇s output is 2.1 ps. The PLL core occupies an area of 0.12 mm2, one fourth of which is occupied by the MiM loop capacitors. The total current consumption of the chip is 16.5 mA. The chip has been sent for fabrication in 0.13 μm complementary metal oxide semiconductor （CMOS） technology.

High-frequency enhancement-mode millimeterwave AlGaN/GaN HEMT with an fT/fmax over 100 GHz/200 GHz

Ultra-thin barrier(UTB) 4-nm-Al Ga N/Ga N normally-off high electron mobility transistors(HEMTs) having a high current gain cut-off frequency( fT) are demonstrated by the stress-engineered compressive Si N trench technology.The compressive in-situ Si N guarantees the UTB-Al Ga N/Ga N heterostructure can operate a high electron density of1.27×1013 cm-2, a high uniform sheet resistance of 312.8 Ω/, but a negative threshold for the short-gate devices fabricated on it. With the lateral stress-engineering by full removing in-situ Si N in the 600-nm Si N trench, the short-gated(70 nm) devices obtain a threshold of 0.2 V, achieving the devices operating at enhancement-mode(E-mode). Meanwhile,the novel device also can operate a large current of 610 m A/mm and a high transconductance of 394 m S/mm for the Emode devices. Most of all, a high fT/fmax of 128 GHz/255 GHz is obtained, which is the highest value among the reported E-mode Al Ga N/Ga N HEMTs. Besides, being together with the 211 GHz/346 GHz of fT/fmax for the D-mode HEMTs fabricated on the same materials, this design of E/D-mode with the realization of fmax over 200 GHz in this work is the first one that can be used in Q-band mixed-signal application with further optimization. And the minimized processing difference between the E-and D-mode designs the addition of the Si N trench, will promise an enormous competitive advantage in the fabricating costs.