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Design and verification of a 10-bit 1.2-V 100-MSPS D/A IP core based on a 0.13-μm low power CMOS process 被引量:2
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作者 徐步陆 邵博闻 +2 位作者 林霞 易伟 刘芸 《Journal of Semiconductors》 EI CAS CSCD 北大核心 2010年第9期99-103,共5页
Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q;random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog conver... Based on a low supply voltage curvature-compensated bandgap reference and central symmetry Q;random walk NMOS current source layout routing method,a 1.2-V 10-bit 100-MSPS CMOS current-steering digital-to-analog converter is implemented in a SMIC 0.13-μm CMOS process.The total consumption is only 10 mW from a single 1.2-V power supply,and the integral and differential nonlinearity are measured to be less than 1 LSB and 0.5 LSB, respectively.When the output signal frequency is 1-5 MHz at 100-MSPS sampling rate,the SFDR is measured to be 70 dB.The die area is about 0.2 mm;. 展开更多
关键词 current-steering digital-to-analog converter low power matching error current source array mixedsignal integrated circuits
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