Decoding of Factorial Experimental Design Models Implemented in Production Process

The paper deals with factorial experimental design models decoding.For the ease of calculation of the experimental mathematical models,it is convenient first to code the independent variables.When selecting independent variables,it is necessary to take into account the range covered by each.A wide range of choices of different variables is presented in this paper.After calculating the regression model,its variables must be returned to their original values for the model to be easy recognized and represented.In the paper,the procedures of simple first order models,with interactions and with second order models,are presented,which could be a very complicated process.Models without and with the mutual influence of independent variables differ.The encoding and decoding procedure on a model with two independent first-order parameters is presented in details.Also,the procedure of model decoding is presented in the experimental surface roughness parameters models’determination,in the face milling machining process,using the first and second order model central compositional experimental design.The simple calculation procedure is recommended in the case study.Also,a large number of examples using mathematical models obtained on the basis of the presented methodology are presented throughout the paper.

Coding of Topological Entities in Feature-Based Parametric Modeling System

How to identify topological entities during rebuilding features is a critical problem in Feature-Based Parametric Modeling System (FBPMS). In the article, authors proposes a new coding approach to distinguish different entities. The coding mechanism is expatiated,and some typical examples are presented. At last, the algorithm of decoding is put forward based on set theory.

APPLICATION OF NEURAL NETWORK INVERSE CONTROL SYSTEM IN TURBO DECODING

Adaptive inverse control system can improve the performance of turbo decoding,and modeling turbo decoder is one of the most important technologies. A neural network model for the inverse model of turbo decoding is proposed in this paper. Compared with linear filter with its revi-sion,the general relationship between the input and output of the inverse model of turbo decoding system can be established exactly by Nonlinear Auto-Regressive eXogeneous input (NARX) filter. Combined with linear inverse system,it has simpler structure and costs less computation,thus can satisfy the demand of real-time turbo decoding. Simulation results show that neural network in-verse control system can improve the performance of turbo decoding further than other linear con-trol system.

一种低复杂度的LDPC码改进型UMP BP-Based译码算法

为了弥补UMP BP-Based相对于LLR BP译码算法的性能缺陷,提出一种改进型UMP BP-Based译码算法。通过将Normalized BP-Based和O ffset BP-Based译码算法的优点相结合,并利用最小均方误差准则来计算该算法中的参数。仿真结果表明,在相同误码率的情况下,改进型UMP BP-Based译码算法比UMP BP-Based、Nor-malized BP-Based以及O ffset BP-Based具有更好的LDPC译码性能。

基于改进型UMP BP-Based算法的LDPC译码研究

为了弥补UMPBP-Based译码算法相对于LLRBP译码算法的性能缺陷,提出一种改进型UMP BP-Based译码算法。该算法中的参数是在最小均方误差准则下确定的,对所有的LDPC码的译码具有通用性。仿真结果表明,在相同误码率的情况下,改进型UMP BP-Based译码算法比UMP BP-Based译码算法、Normalized BP-Based译码算法以及Offset BP-Based译码算法具有更好的LDPC译码性能。

一种非规则LDPC码的改进型UMPBP-Based译码算法

为了减小UMP BP-Based译码算法相对于LLR-BP译码算法的性能损失,提出了一种改进型UMP BP-Based译码算法,校验节点消息处理时,通过合理地设置校正因子与偏移因子2种参数,将Normalized BP-Based和Offset BP-Based 2种译码算法进行有效的融合;变量节点消息处理时,引入了一种LLR-BP译码算法中的震荡补偿算法.仿真结果表明,针对非规则LDPC码,在一定范围内误码率相同的条件下,改进型UMP BP-Based译码算法与UMP BP-Based、Normalized BP-Based和Offset BP-Based 3种译码算法相比较,译码性能得到明显的改善,可以更有效地逼近性能优异的LLR-BP译码算法.

Efficient VLSI architecture of CAVLC decoder with power optimized

This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore＇s decoding, arithmetic operation is combined with finite state machine （FSM）, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

High throughput VLSI architecture for H.264/AVC context-based adaptive binary arithmetic coding(CABAC) decoding

Context-based adaptive binary arithmetic coding(CABAC) is the major entropy-coding algorithm employed in H.264/AVC.In this paper,we present a new VLSI architecture design for an H.264/AVC CABAC decoder,which optimizes both decode decision and decode bypass engines for high throughput,and improves context model allocation for efficient external memory access.Based on the fact that the most possible symbol(MPS) branch is much simpler than the least possible symbol(LPS) branch,a newly organized decode decision engine consisting of two serially concatenated MPS branches and one LPS branch is proposed to achieve better parallelism at lower timing path cost.A look-ahead context index(ctxIdx) calculation mechanism is designed to provide the context model for the second MPS branch.A head-zero detector is proposed to improve the performance of the decode bypass engine according to UEGk encoding features.In addition,to lower the frequency of memory access,we reorganize the context models in external memory and use three circular buffers to cache the context models,neighboring information,and bit stream,respectively.A pre-fetching mechanism with a prediction scheme is adopted to load the corresponding content to a circular buffer to hide external memory latency.Experimental results show that our design can operate at 250 MHz with a 20.71k gate count in SMIC18 silicon technology,and that it achieves an average data decoding rate of 1.5 bins/cycle.

电力线信道中极化码译码算法的改进

脉冲噪声是影响电力线通信性能的最主要因素。为了提升极化码在电力线信道的性能,文章提出了分段循环冗余校验码辅助串行抵消列表比特翻转(segmented CRC aid SCL-bit flip,SCA-SCL-BF)译码算法,并在加性高斯白噪声(additive white gaussian noise,AWGN)信道和电力线信道下进行了仿真。在构造关键集合时引入Rate1子块,避免了全集搜索的复杂度;根据关键集合中比特的位置进行分段,每段翻转一比特,可以实现多比特翻转。仿真结果表明,SCA-SCL-BF算法的性能相较于公开文献中性能在信噪比(signal-to-noiseratios,SNR)大于0dB时有显著提升。该算法对于提升电力线传输性能有重要意义。

基于Matlab的运动控制系统实验平台设计

针对运动控制系统课程在传统教学中,学生在课程理论知识学习和利用Matlab/Simulink仿真阶段,缺少实际控制单元设计与开发实际工程训练的问题,设计了一个基于Matlab的运动控制系统实验平台,在实验平台使用基于模型设计的方法可实现从仿真测试到实物测试一体化;通过介绍实验平台中的PC端环境配置流程以及实验平台中驱动器的构成给出了实验平台的总体设计方案;说明了实验平台应用基于模型设计的方法实现代码自动生成的流程,并对基于模型设计的开发流程进行了详细的阐述;通过案例永磁同步电机转速、电流双闭环控制系统在实验平台经过模型在环仿真、软件在环仿真、处理器在环仿真,最后到实验平台进行实物测试的流程与实验结果来达到验证实验平台的优点及其可行性和有效性的目的。

航天地面站低代码开发平台方案设计

为了满足新形势下航天地面站快速交付、灵活部署与升级的需求,分析了基于模型的系统工程(Model-based Systems Engineering,MBSE)的航天地面系统模型,设计了一种适用于航天地面系统的低代码开发平台。该平台基于MBSE模型并通过可视化接口来构建包含软件功能、运行流程、数据处理等内容的应用程序。应用低代码软件平台,降低了软件开发的复杂性,满足装备快速升级的需求,研制时间较传统方法缩短了近45%。

Reduce the decoding complexity: segment linear network coding

The throughput gain obtained by linear network coding （LNC） grows as the generation size increases, while the decoding complexity also grows exponentially. High decoding complexity makes the decoder to be the bottleneck for high speed and large data transmissions. In order to reduce the decoding complexity of network coding, a segment linear network coding （SLNC） scheme is proposed. SLNC provides a general coding structure for the generation-based network coding. By dividing a generation into several segments and restraining the coding coefficients of the symbols within the same segment, SLNC splits a high-rank matrix inversion into several low-rank matrix inversions, therefore reduces the decoding complexity dramatically. In addition, two coefficient selection strategies are proposed for both centrally controlled networks and distributed networks respectively. The theoretical analysis and simulation results prove that SLNC achieves a fairly low decoding complexity at a cost of rarely few extra transmissions.

基于MBD的PLC运动控制系统设计与应用

针对复杂算法在PLC运动控制系统中难以工程实现的问题,该文提出了一种基于MBD(model based design)的系统设计和应用方法。首先,利用MATLAB/Simulink建立控制模型并仿真验证,预留变量接口,正确匹配参数定义和数据类型;然后,基于Simulink PLC Coder将模型转换为符合IEC 61131-3标准的结构化文本ST(structure text)代码,根据集成开发环境CoDeSys定制文件格式;最后,将生成代码以功能块FB(function block)的形式导入CoDeSys,实现算法与应用程序的集成。某型起重机回转控制系统的应用证明了MBD方法可有效解决复杂算法工程实现难的问题。

基于概率主题模型的软件开发数据库隐私数据泄露识别方法研究

为了提升软件开发数据库的隐私数据安全性,提出基于概率主题模型的软件开发数据库隐私数据泄露识别方法。挖掘“主题-词”与“主题-文档”之间的概率分布,建立概率主题模型,通过该模型将数据转化为恶意代码并提取特征;同时结合概率检测算法与指纹对比判断恶意代码配置文件是否为敏感文件,将敏感恶意代码配置文件主题上的概率均值作为确定隐私数据泄漏的指标,实现隐私数据泄露识别。实验结果表明,该方法可100%识别软件开发数据库的隐私数据是否泄漏,而且针对不同欺骗率和失真率的网络攻击导致的软件开发数据库的隐私数据泄露,识别准确率依旧在98%以上,泄露识别优势显著。

Model-Based Embedded Compiled Software Fault Positioning

Software fault positioning is one of the most effective activities in program debugging. In this paper, we propose a model-based fault positioning method to detect the faults of embedded program without source code. The system takes the machine code of embedded software as input and translates the code into high-level language C with the software reverse engineering program. Then, the static analysis on the high-level program is taken to obtain a control flow graph（CFG）, which is denoted as a node-tree and each node is a basic block. According to the faults found by the field testing, we construct a fault model by extracting the features of the faulty code obtained by ranking the Ochiai coefficient of basic blocks. The model can be effectively used to locate the faults of the embedded program. Our method is evaluated on ST chips of the smart meter with the corresponding source code. The experiment shows that the proposed method has an effectiveness about 87% on the fault detection.

LDPC码串行译码策略的收敛速度分析

基于校验节点分组的LDPC码串行译码策略具有很高的收敛速度,但当分组数过多,并行度过低时译码时延很大.针对此问题,利用外信息转移(EXIT)图技术找到收敛速度和译码时延的平衡点.首先推导不同分组数下串行译码策略的EXIT函数,然后通过比较函数对应的EXIT曲线估计出在不牺牲收敛速度的前提下该策略能达到的最大并行度.仿真结果验证了EXIT图分析的正确性.

LDPC码的高效译码算法研究

对于LDPC码的译码算法即和积算法,目前的简化算法多在对数域中进行。提出了一种新的基于差分的译码算法,其主要思想是:在LDPC码的二部图上所传递的消息是概率的差分值,而对于校验节点和消息节点的更新都是在特定的加法域中进行。针对校验节点的更新,还可以选择若干个绝对值最小的差分值进行运算,以进一步降低复杂度。与传统的基于对数似然比的译码方法相比,该算法的计算复杂度有很大降低,而译码性能和收敛速度没有明显损失。

参数化特征造型中拓扑实体的编码方法探讨

特征造型中的一个关键问题是特征重构时如何有效识别特征所依赖的拓扑实体 ,本文采用编码记录不同的拓扑实体在特征链中的相对位置 ,从理论和实践两方面阐述了编码的思想和实际应用 ,并提出了以集合为基础 的译码算法。

程序流程图到代码的自动生成算法

提出了一种从标准程序流程图到结构化代码生成的新算法.该算法通过对程序流程图结构的分析与识别、循环结构的线性化以及对分支结构域的确定等过程,能够生成符合程序流程图语义的结构化C代码(包括continue/break/return);同时,能够识别出非结构化的程序流程图.

三角形网格基活动图像编码研究——基本框架和I帧编码

本文结合实验结果,深入讨论了三角形网格基活动图像编码方法的基本框架和帧内编码问题。文中全面比较了DTM+MD的帧内编码方法和JPEG方法的性能,表明采用DTM+MD作帧内编码具有更好的主客观质量。