Stochastic resonance in a monostable system driven by square-wave signal and dichotomous noise

This paper investigates the stochastic resonance in a monostable system driven by square-wave signal, asymmetric dichotomous noise as well as by multiplicative and additive white noise. By the use of the properties of the dichotomous noise, it obtains the expressions of the signal-to-noise ratio under the adiabatic approximation condition. It finds that the signal-to-noise ratio is a non-monotonic function of the asymmetry of the dichotomous noise, and which varies non- monotonously with the intensity of the multiplicative and additive noise as well as the system parameters. Moreover, the signal-to-noise ratio depends on the correlation rate and intensity of the dichotomous noise.

Structure and design method for pulse-triggered flip-flops at switch level

A kind of structure and a design method using transmission voltage-switch theory for pulse-triggered flip-flops were proposed,which are suitable for all kinds of pulse-triggered flip-flops and no extra techniques are needed to eliminate the switching activities of internal nodes.Based on the proposed structure and design technique,two pulsed flip-flops were implemented and simulated.The proposed pulsed flip-flops have simple circuit structures.HSPICE simulation shows that the proposed pulsed D flip-flop outperforms the conventional pulsed D flip-flop by 17.2% in delay and 30.1% in power-delay-product(PDP) and the proposed pulsed JK flip-flop has low power and small PDP compared with pulsed D pulsed flip-flops,confirming that the proposed structure and design technique are simple and practical.

DESIGN OF nMOS QUATERNARY FLIP-FLOPS AND THEIR APPLICATIONS

By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed. These flip-flops have the capability of two-input presetting and double-rail complementary outputs. It is shown that these flip-flops are effectively suitable to design nMOS quaternary sequential circuits by designing two examples of hexadecimal up-counter and decimal up-counter.

A FAULT DETECTION SENSOR FOR CIRCUIT AGING USING DOUBLE-EDGE-TRIGGERED FLIP-FLOP

In nanoscale technology, transistor aging is one of the most critical problems that impact on the reliability of circuits. Aging sensor is a good online way to detect the circuit aging, which performs during the operating time with no influence of the normal operation of circuits. In this paper, a Dou- ble-edge-triggered Detection Sensor for circuit Aging （DSDA） is proposed, which employs data signal of logic circuits as its clock to control the sampling process. The simulation is done by Hspice using 45 nm technology. The results show that this technique is not case of the detection precision is more than 80% under aging fault effectively with the 8% power cost and 30% sensitive to the process variations. The worst the different process variations. It can detect performance cost.

On Switching of a Flip-Flop Jet Nozzle with Double Ports by Single-Port Control

This research deals with the oscillation mechanism of a flip-flop jet nozzle with a connecting tube, based on the measurements of pressures and velocities in the connecting tube and inside the nozzle. The measurements are carried out varying: 1) the inside diameter d of the connecting tube;2) the length L of the connecting tube and 3) the jet velocity VPN from a primary-nozzle exit. We assume that the jet switches when a time integral reaches a certain value. At first, as the time integral, we introduce the accumulated flow work of pressure, namely, the time integral of mass flux through a connecting tube into the jet-reattaching wall from the opposite jet-un-reattaching wall. Under the assumption, the trace of pressure difference between both the ends of the connecting tube is simply modeled on the basis of measurements, and the flow velocity in the connecting tube is computed as incompressible flow. Second, in order to discuss the physics of the accumulated flow work further, we conduct another experiment in single-port control where the inflow from the control port on the jet-reattaching wall is forcibly controlled and the other control port on the opposite jet-un-reattaching wall is sealed, instead of the experiment in regular jet’s oscillation using the ordinary nozzle with two control ports in connection. As a result, it is found that the accumulated flow work is adequate to determine the dominant jet- oscillation frequency. In the experiment in single-port control, the accumulated flow work of the inflow until the jet’s switching well agrees with that in regular jet’s oscillation using the ordinary nozzle.

RESEARCH INTO TERNARY EDGE-TRIGGERED JKL FLIP-FLOP

The design of ternary edge-triggered JKL-type flip-flop is proposed.The computersimulation and the test in experimental circuit made up with TTL gate show this flip-flop has theexpected logic functions.

DESIGN OF TERNARY FLIP-FLOPS AND SEQUENTIAL CIRCUITS BASED UPON U_h GATE

According to the next-state equations of various ternary flip-flops(tri-flop),whichare based upon ternary modular algebra,various ternary flip-flops are implemented by usinguniversal-logic-modules,U_hs.Based on it,ternary sequential circuits are implemented by usingarray of universal-logic-modules,U_hs.

Low power and high speed explicit-pulsed double-edge triggered level converting flip-flop

Variable supply voltage-clustered voltage scaling （VS-CVS） scheme can be very effective in reducing power consumption of CMOS circuits without degrading system performance. Level converting flip-flops （LCFFs） are key elements in the CVS scheme. In this paper, a new explicit-pulsed double-edge triggered level converting flip-flop （nEP-DET-LCFF） is proposed, which employs double-edge triggering technique, dynamic structure, explicit pulse generator, conditional discharge technique and proper arrangement of stacked nMOS transistors to efficiently perform latching and level converting functions simultaneously. The proposed nEP-DET-LCFF combines merits of both conventional explicit-LCFFs and implicit-LCFFs. Simulation shows the proposed nEP-DET-LCFF has improvement of 19.2% -46% in delay, and 19.4% - 52.9% in power-delay product （PDP） as compared with the published LCFFs.

An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies(Invited paper)

Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.

Flip-Flop Flow Control inside Streamwise Diverging Diamond-Shaped Cylinder Bundles with Concavities

The flow visualization work with the aid of PIV and Piezometer deals with flip-flop flow around diamond-shaped cylinder bundle revised with concavities on both bundle walls. It is disclosed that 1) the concavity constructed on both side-walls of a diamond cylinder induces a substantial change in the flow patterns in the exit jet-stream field and jet- stream dispersion, 2) pressure characteristics are quantitatively measured in a diverging-flow region in diamond cylinder bundles with concavityand in its downstream region, and 3) flip-flop flow occurs in the flow passages and its occurrence condition is obtained.

Numerical Simulation of an All Optical Flip-Flop Based on a Nonlinear Distributed Bragg Reflector Laser Structure

A new design for an all optical flip flop is introduced. It is based on a nonlinear Distributed Bragg Reflector (DBR) semiconductor laser structure. The device does not require a holding beam. An optical gain medium confined between 2 Bragg reflectors forms the device. One of the Bragg reflectors is detuned from the other by making its average refractive index slightly higher, and it has a negative nonlinear coefficient that is due to direct absorption at Urbach tail. At low light intensity in the structure, the detuned Bragg reflector does not provide optical feedback to start a laser mode. An optical pulse injected to the structure reduces the detuning of the nonlinear Bragg reflector and a laser mode builds up. The device is reset by detuning the second Bragg reflector optically by an optical pulse that generates electron-hole pairs by direct absorption. A mathematical model of the device is introduced. The model is solved numerically in time domain using a general purpose graphics processing unit (GPGPU) to increase accuracy and to reduce the computation time. The switching dynamics of the device are in nanosecond time scale. The device could be used for all optical data packet switching/routing.

An Improved Design for an All-Optical Flip-Flop Based on a Nonlinear 3-Sections DFB Laser Cavity

A new all optical flip-flop based on a 3-sections nonlinear semiconductor DFB laser structure is proposed and simulated. The operation of the device does not require a holding beam. Electrical current injection into an active layer provides optical gain to the laser mode. The wave-guiding layer consists of a linear grating section centered between 2 detuned nonlinear grating sections. The average refractive index in the nonlinear sections is slightly higher than the refractive index of the middle section. A negative nonlinear refractive index coefficient exists along the nonlinear sections. In the “OFF” state, the DFB structure does not provide enough optical feedback to lase due to the detuned sections. At high light intensity in structure, “ON” state, detuning decreases and the DFB structure allows for a laser mode that sustains the decrease in detuning to exist. The nonlinearity is provided by direct photon absorption at the Urbach tail. Numerical simulations using GPGPU computing show nanoseconds transition times between “OFF” and “ON” states.

Simulations of a Novel All-Optical Flip-Flop Based on a Nonlinear DFB Laser Cavity Using GPGPU Computing

A new all-optical flip-flop based on a nonlinear Distributed feedback (DFB) structure is proposed. The device does not require a holding beam. A nonlinear part of the grating is detuned from the remaining part of the grating and has negative nonlinear coefficient. Optical gain is provided by an injected electrical current into an active layer. In the OFF state, due to the detuned section, no laser light is generated in the device. An injected optical pulse reduces the detuning of the nonlinear section, and the optical feedback provided by the DFB structure generates a laser light in the structure that sustains the change in the detuned section. The device is switched “OFF” by detuning another section of the grating by a Reset pulse. The Reset pulse reduces the refractive index of that section by the generation of electron-hole pairs. The Reset pulse wavelength is adjusted such that the optical gain provided by the active layer at that wavelength is zero. The Reset pulse is prevented from reaching the nonlinear detuned section by introducing an optical absorber in the laser cavity to attenuate the pulse. The device is simulated in time domain using General Purpose Graphics Processing Unit (GPGPU) computing. Set-Reset operations are in nanosecond time scale.

An Improved Power Efficient Clock Pulsed D Flip-flop Using Transmission Gate

Recent digital applications will require highly efficient and high-speed gadgets and it is related to the minimum delay and power consumption.The proposed work deals with a low-power clock pulsed data flip-flop(D flip-flop)using a transmission gate.To accomplish a power-efficient pulsed D flip-flop,clock gating is proposed.The gated clock reduces the unnecessary switching of the transistors in the circuit and thus reduces the dynamic power consumption.The clock gating approach is employed by using an AND gate to disrupt the clock input to the circuit as per the control signal called Enable.Due to this process,the clock gets turned off to reduce power consumption when there is no change in the output.The proposed transmission gate-based pulsed D flip-flop’s performance with clock gating and without clock gating circuit is analyzed.The proposed pulsed D flip-flop power consumption is 1.586μw less than the without clock gated flip-flop.Also,the authors have designed a 3-bit serial-in and parallel-out shift register using the proposed D flip-flop and analyzed the performance.Tanner Electronic Design Automation tool is used to simulate all the circuits with 45 nm technology.

多种模式降水预报的稳定性特征研究

预报的稳定性是指对同一时段在不同时间发布的多时效预报结论的一致性,是模式预报质量的一个重要方面,较大的不稳定性会给使用者造成困扰。为深入了解业务常用模式的稳定性,使用相对标准偏差指标计算不同时效预报的降水量波动大小,并改进了Flip-Flop指数(改进后简称FF_(norm)),计算多时效降水量预报变化趋势的翻转程度,衡量预报变化趋势的稳定性,对2种全球模式(ECMWF、NCEP-GFS)、3种区域模式(CMA-MESO、CMA-SH9、HHUPS-ST),在中国6个气候分区中降水预报的稳定性进行对比分析,分为实况有降水和暴雨及以上降水2种情况进行了讨论。结果表明:实况有降水时,相对区域模式来说,全球模式的多时效降水预报的相对标准偏差较小,即模式降水量预报的波动较小;各模式对西南区的西部、东北区的东部以及华南区的南部预报的波动性相对较小,西北区的西部波动性较大。就多时效降水量预报变化趋势而言,2种情况下均为CMA-MESO、NCEP-GFS和ECMWF的稳定性较好,其FF_(norm)指数小于HHUPS-ST和CMA-SH9模式,其中CMA-MESO对西南区、华南部分地区降水量预报变化趋势的稳定性较为突出;CMA-SH9的指数最大,多时效降水量预报变化趋势稳定性较差;各模式对长江中下游地区的FF norm指数相对较大,多时效预报趋势的稳定性较差。有降水时,CMA-MESO随时效临近的降水量预报变化趋势稳定(单调递增、单调递减或不变)的频次最多,其次是NCEP-GFS,2种降水情况下,该2种模式的降水量预报均为随时效临近单调递增次数大于递减次数,且CMA-MESO单调递增特征尤其显著。以上特征能够为模式调试和预报决策提供参考。

α稳定噪声下时滞非对称单稳系统的随机共振

将α稳定噪声与单稳系统相结合,分别研究了不同α稳定噪声环境下的无时滞项和有时滞项的非对称单稳系统的随机共振。利用数值仿真说明了在无时滞项和有时滞项的非对称单稳系统中均存在随机共振现象,并讨论了α稳定噪声特征指数α(0<α≤2)、对称参数β(-1≤β≤1)、单稳系统参数a、乘性噪声放大系数D、非对称系数r及时滞量τ对系统信噪比增益的影响。

采用粒子群算法的冲击信号自适应单稳态随机共振检测方法

针对冲击信号阱内共振的特点、随机共振系统参数合理选取缺乏有效的理论依据以及传统自适应随机共振单参数优化的不足,提出一种基于粒子群算法(Particle swarm optimization,PSO)的多参数同步优化自适应单稳态随机共振方法。该方法采用单稳态随机共振模型,避免了经典双稳系统势阱间的共振跃迁,并选用单稳态系统输出的加权峭度指标作为PSO的适应度函数,能够实现多参数的同步自适应选取,从而最优地检测出原始信号中的冲击成分。将PSO和变尺度随机共振相结合,并给出冲击信号自适应随机共振算法流程。该算法被用于仿真冲击信号与工程实际中冲击信号的检测,结果表明所提方法简单易行,收敛速度快,能够有效提高信噪比,具有良好的工程应用前景。

一种基于信号补偿的频率测量方法

提出一种通过对被测信号脉宽进行补偿处理以提高频率测量精确度的方法。采用多路单稳态脉冲信号作为补偿信号分别对被测信号脉宽补偿,各组补偿信号脉宽均匀递增且增量总和为一个基准信号周期,选取被测信号补偿后对应的基准信号计数值跳变时刻前后相邻的2组补偿信号脉宽平均值作为理想补偿信号脉宽,最后根据补偿后被测信号和理想补偿信号脉宽获得被测信号的频率。误差分析和测量不确定度评定表明该方法测量精确度由相邻补偿信号间的脉宽增量决定。实验数据证明该方法在保证测量速度的同时有效减小了频率测量中固有的1个基准信号周期的测量误差。

随机共振降噪下的齿轮微弱故障特征提取

针对强背景噪声下的齿轮微弱故障特征提取问题,提出了一种将级联单稳随机共振与经验模式分解(EMD)-Teager能量算子解调方法相结合的特征提取方法。首先对含噪故障信号进行随机共振输出,降噪后再进行经验模式分解,分解得到具有不同特征时间尺度的固有模态函数(IMFs),最后通过Teager能量算子解调方法求取每个有效IMF分量的幅频信息,从而提取齿轮微弱故障特征。仿真分析和实际测试结果均表明,通过随机共振降噪后,该方法能有效检测出齿轮局部损伤故障特征频率。

用可编程逻辑器件实现单稳态触发器

可编程逻辑器件一般用于完成数字电路的功能。对用可编程逻辑器件技术实现模拟集成电路的功能进行了探讨 ,研究了实现单稳态触发器脉冲宽度控制的两种方法 :用外接RC的单稳态触发器 ;用外部信号控制脉宽。实验结果表明在全数字电路的基础上 ,用可编程逻辑器件实现的单稳态触发器脉宽控制能有效地实现激光引信电路系统小型化 。