A low-power and low-energy flexible GF(p) elliptic-curve cryptography processor

We investigate the use of two integer inversion algorithms,a modified Montgomery modulo inverse and a Fermat's Little Theorem based inversion,in a prime-field affine-coordinate elliptic-curve crypto-processor.To perform this,we present a low-power/energy GF(p) affine-coordinate elliptic-curve cryptography(ECC) processor design with a simplified architecture and complete flexibility in terms of the field and curve parameters.The design can use either of the inversion algorithms.Based on the implementations of this design for 168-,192-,and 224-bit prime fields using a standard 0.13 μm CMOS technology,we compare the efficiency of the algorithms in terms of power/energy consumption,area,and calculation time.The results show that while the Fermat's theorem approach is not appropriate for the affine-coordinate ECC processors due to its long computation time,the Montgomery modulo inverse algorithm is a good candidate for low-energy implementations.The results also show that the 168-bit ECC processor based on the Montgomery modulo inverse completes one scalar multiplication in only 0.4 s at a 1 MHz clock frequency consuming only 12.92 μJ,which is lower than the reported values for similar designs.

Secure and Energy Efficient Design of Multi-Modular Exponential Techniques for Public-Key Cryptosystem

The present paper proposes a secure design of the energy-efficient multi-modular exponential techniques that use store and reward method and store and forward method.Computation of the multi-modular exponentiation can be performed by three novel algorithms:store and reward,store and forward 1-bit(SFW1),and store and forward 2-bit(SFW2).Hardware realizations of the proposed algorithms are analyzed in terms of throughput and energy.The experimental results show the proposed algorithms SFW1 and SFW2 increase the throughput by orders of 3.98% and 4.82%,reducing the power by 5.32% and 6.15% and saving the energy in the order of 3.95% and 4.75%,respectively.The proposed techniques can prevent possible side-channel attacks and timing attacks as a consequence of an inbuilt confusion mechanism.Xilinx Vivado-21 on Virtex-7 evaluation board and integrated computer application for recognizing user services(ICARUS)Verilog simulation and synthesis tools are used for field programmable gate array(FPGA)for hardware realization.The hardware compatibility of proposed algorithms has also been checked using Cadence for application specific integrated circuit(ASIC).