基于DCNv2和Transformer Decoder的隧道衬砌裂缝高效检测模型研究

为解决因衬砌裂缝性状随机、分布密集、标注框分辨率低所导致的现有模型识别精度低、检测速度慢及参数量庞大等问题,以第2版可变形卷积网络(DCNv2)和端到端变换器解码器(Transformer Decoder)为基础对YOLOv8网络框架进行改进,提出了面向衬砌裂缝的检测模型DTD-YOLOv8。首先,通过引入DCNv2对YOLOv8主干卷积网络C2f进行融合以实现模型对裂缝形变特征的准确快速感知,同时采用Transformer Decoder对YOLOv8检测头进行替换以实现端到端框架内完整目标检测流程,从而消除因Anchor-free处理模式所带来的计算消耗。采用自建裂缝数据集对SSD,Faster-RCNN,RT-DETR,YOLOv3,YOLOv5,YOLOv8和DTD-YOLOv8的7种检测模型进行对比验证。结果表明:改进模型F1分数和mAP@50值分别为87.05%和89.58%;其中F1分数相较其他6种模型分别提高了14.16%,7.68%,1.55%,41.36%,8.20%和7.40%;mAP@50分别提高了28.84%,15.47%,1.33%,47.65%,10.14%和10.84%。改进模型参数量仅为RT-DETR的三分之一,检测单张图片的速度为16.01 ms,FPS为65.46帧每秒,对比其他模型检测速度得到提升。该模型在面向运营隧道裂缝检测任务需求时能够表现出高效的性能。

Parallel Implementation of the CCSDS Turbo Decoder on GPU

This paper presents a software turbo decoder on graphics processing units(GPU).Unlike previous works,the proposed decoding architecture for turbo codes mainly focuses on the Consultative Committee for Space Data Systems(CCSDS)standard.However,the information frame lengths of the CCSDS turbo codes are not suitable for flexible sub-frame parallelism design.To mitigate this issue,we propose a padding method that inserts several bits before the information frame header.To obtain low-latency performance and high resource utilization,two-level intra-frame parallelisms and an efficient data structure are considered.The presented Max-Log-Map decoder can be adopted to decode the Long Term Evolution(LTE)turbo codes with only small modifications.The proposed CCSDS turbo decoder at 10 iterations on NVIDIA RTX3070 achieves about 150 Mbps and 50Mbps throughputs for the code rates 1/6 and 1/2,respectively.

Quantized Decoders that Maximize Mutual Information for Polar Codes

In this paper,we innovatively associate the mutual information with the frame error rate(FER)performance and propose novel quantized decoders for polar codes.Based on the optimal quantizer of binary-input discrete memoryless channels(BDMCs),the proposed decoders quantize the virtual subchannels of polar codes to maximize mutual information(MMI)between source bits and quantized symbols.The nested structure of polar codes ensures that the MMI quantization can be implemented stage by stage.Simulation results show that the proposed MMI decoders with 4 quantization bits outperform the existing nonuniform quantized decoders that minimize mean-squared error(MMSE)with 4 quantization bits,and yield even better performance than uniform MMI quantized decoders with 5 quantization bits.Furthermore,the proposed 5-bit quantized MMI decoders approach the floating-point decoders with negligible performance loss.

基于ML-Decoder多分量雷达信号脉内调制识别方法

在现代电子侦察领域,由于电磁环境复杂,脉冲流密度较大,存在同时接收多个雷达信号的情况,多个雷达信号会在时域和频域出现重叠问题,使得雷达信号的特征变得混淆复杂。雷达信号的脉冲调制识别研究在单分量信号中取得了较好的效果,而在多分量雷达信号领域中,需要更多创新方法。为了解决上述问题,提出基于多标签解码器网络(Multi-Lable Decoder Network)框架。该网络框架首先用Choi-Williams分布(Choi-Williams Distribution,CWD)将一维信号转变为时频图。然后通过卷积神经网络提取特征,将提取的特征和查询向量一起送进decoder分类器中。decoder分类器通过标签查询的方法匹配特征信息,有效地避免传统卷积神经网络通过全局池化而淹没丰富的特征。用该方法对由六种典型雷达信号随机组成的多分量雷达信号经行调制识别分析,平均识别准确率达到93.9%,优于所对比的其他深度学习算法。

Area optimization of parallel Chien search architecture for Reed-Solomon(255,239) decoder

A global optimization algorithm （GOA） for parallel Chien search circuit in Reed-Solomon （RS） （255,239） decoder is presented. By finding out the common modulo 2 additions within groups of Galois field （GF） multipliers and pre-computing the common items, the GOA can reduce the number of XOR gates efficiently and thus reduce the circuit area. Different from other local optimization algorithms, the GOA is a global one. When there are more than one maximum matches at a time, the best match choice in the GOA has the least impact on the final result by only choosing the pair with the smallest relational value instead of choosing a pair randomly. The results show that the area of parallel Chien search circuits can be reduced by 51% compared to the direct implementation when the group-based GOA is used for GF multipliers and by 26% if applying the GOA to GF multipliers separately. This optimization scheme can be widely used in general parallel architecture in which many GF multipliers are involved.

A Total Dose Radiation Hardened PDSOI CMOS 3-Line to 8-Line Decoder

The first domestic total dose hardened 2μm partially depleted silicon-on-insulator （PDSOI） CMOS 3-line to 8- line decoder fabricated in SIMOX is demonstrated. The radiation performance is characterized by transistor threshold voltage shifts,circuit static leakage currents,and I-V curves as a function of total dose up to 3× 10^5rad（Si）. The worst case threshold voltage shifts of the front channels are less than 20mV for nMOS transistors at 3 × 10^5rad（Si） and follow-up irradiation and less than 70mV for the pMOS transistors. Furthermore, no significant radiation induced leakage currents and functional degeneration are observed.

基于encoder-decoder框架的城镇污水厂出水水质预测

由于污水厂的出水水质指标繁多、污水处理过程中反应复杂、时序非线性程度高,基于机理模型的预测方法无法取得理想效果。针对此问题,提出基于深度学习的污水厂出水水质预测方法,并以吉林省某污水厂监测水质为来源数据,利用多种结合encoder-decoder结构的神经网络预测水质。结果显示,所提结构对LSTM和GRU网络预测能力都有一定提升,对长期预测能力提升更加显著,ED-GRU模型效果最佳,短期预测中的4个出水水质指标均方根误差(RMSE)为0.7551、0.2197、0.0734、0.3146,拟合优度(R2)为0.9013、0.9332、0.9167、0.9532,可以预测出水质局部变化,而长期预测中的4个指标RMSE为1.7204、1.7689、0.4478、0.8316,R2为0.4849、0.5507、0.4502、0.7595,可以预测出水质变化趋势,与顺序结构相比,短期预测RMSE降低10%以上,R2增加2%以上,长期预测RMSE降低25%以上,R2增加15%以上。研究结果表明,基于encoder-decoder结构的神经网络可以对污水厂出水水质进行准确预测,为污水处理工艺改进提供技术支撑。

基于时空特征融合的Encoder-Decoder多步4D短期航迹预测

航迹预测在确保空中交通安全、高效运行中扮演着至关重要的角色。所预测的航迹信息是航迹优化、冲突告警等决策工具的输入,而预测准确性取决于模型对航迹序列特征的提取能力。航迹序列数据是具有丰富时空特征的多维时间序列,其中每个变量都呈现出长短期的时间变化模式,并且这些变量之间还存在着相互依赖的空间信息。为了充分提取这种时空特征,本文提出了基于融合时空特征的编码器-解码器(Spatio-Temporal EncoderDecoder,STED)航迹预测模型。在Encoder中使用门控循环单元(Gated Recurrent Unit,GRU)、卷积神经网络(Convolutional Neural Network,CNN)和注意力机制(Attention,AT)构成的双通道网络来分别提取航迹时空特征,Decoder对时空特征进行拼接融合,并利用GRU对融合特征进行学习和递归输出,实现对未来多步航迹信息的预测。利用真实的航迹数据对算法性能进行验证,实验结果表明,所提STED网络模型能够在未来10 min预测范围内进行高精度的短期航迹预测,相比于LSTM、CNN-LSTM和AT-LSTM等数据驱动航迹预测模型具有更高的精度。此外,STED网络模型预测一个航迹点平均耗时为0.002 s,具有良好的实时性。

Modified Benes network architecture for WiMAX LDPC decoder

A modified Benes network is proposed to be used as an optimal shuffle network in worldwide interoperability for microwave access （WiMAX） low density parity check （LDPC） decoders, When the size of the input is not a power of two, the modified Benes network can achieve the most optimal performance. This modified Benes network is non-blocking and can perform any sorts of permutations, so it can support 19 modes specified in the WiMAX system. Furthermore, an efficient algorithm to generate the control signals for all the 2 × 2 switches in this network is derived, which can reduce the hardware complexity and overall latency of the modified Benes network. Synthesis results show that the proposed control signal generator can save 25.4% chip area and the overall network latency can be reduced by 36. 2%.

基于Encoder-Decoder注意力网络的异常驾驶行为在线识别方法

异常驾驶行为是车辆安全运行的重大威胁,其对人员与物资的安全高效投送造成严重危害。以低成本非接触式的手机多传感器数据为基础,通过对驾驶行为特性进行数据分析,提出一种融合Encoder-Decoder深度网络与Attention机制的异常驾驶行为的在线识别方法。该方法由基于LSTM(long short-term memory)的Encoder-Decoder、Attention机制与基于SVM(support vector machine)的分类器3个模块构成。该系统识别方法包括:输入编码、注意力学习、特征解码、序列重构、残差计算与驾驶行为分类等6个步骤。该技术方法利用自然驾驶条件下所采集的手机传感器数据进行实验。实验结果表明:①手机多传感器数据融合方法对驾驶行为识别具备有效性;②异常驾驶行为必然会造成数据异常波动;③Attention机制有助于提升模型学习效果,对所提出模型的识别准确率F1-score为0.717,与经典同类模型比较,准确率得到显著提升;④对于汽车异常驾驶行为来说,SVM比Logistic与随机森林算法具有更优越的识别效果。

Viterbi Decoder ACS单元中路径度量值存储空间的优化

ACS单元的设计及路径度量(PM)值的存储是Viterbi Decoder硬件实现的重要部分之一。介绍了一种码率为1/2的硬判决Viterbi Decoder的ACS部分的硬件实现方法。采用了一种全新的设计与存储方式,即原位运算旋转地址的方式,极大地节省了在ACS运算过程中用以存储路径度量值的RAM空间,大量的实验证明,设计的译码器在资源消耗上有较大优势。

High Performance Viterbi Decoder on Cell/B.E.

Viterbi decoding is widely used in many radio systems. Because of the large computation complexity, it is usually implemented with ASIC chips, FPGA chips, or optimized hardware accelerators. With the rapid development of the multicore technology, multicore platforms become a reasonable choice for software radio (SR) systems. The Cell Broadband Engine processor is a state-of-art multi-core processor designed by Sony, Toshiba, and IBM. In this paper, we present a 64-state soft input Viterbi decoder for WiMAX SR Baseband system based on the Cell processor. With one Synergistic Processor Element (SPE) of a Cell Processor running at 3.2GHz, our Viterbi decoder can achieve the throughput up to 30Mb/s to decode the tail-biting convolutional code. The performance demonstrates that the proposed Viterbi decoding implementation is very efficient. Moreover, the Viterbi decoder can be easily integrated to the SR system and can provide a highly integrated SR solution. The optimization methodology in this module design can be extended to other modules on Cell platform.

Lowering the Error Floor of ADMM Penalized Decoder for LDPC Codes

Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.

Radiation Tolerant Viterbi Decoders for On-Board Processing(OBP) in Satellite Communications

Modern satellite communication systems require on-board processing(OBP)for performance improvements,and SRAM-FPGAs are an attractive option for OBP implementation.However,SRAM-FPGAs are sensitive to radiation effects,among which single event upsets(SEUs)are important as they can lead to data corruption and system failure.This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory.Analysis and fault injection experiments are conducted to verify that over 97%of the SEUs on user memory would not lead to output errors.To achieve a better reliability,selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead.Although the results are obtained for a specific FPGA implementation,the developed reliability estimation model and the general conclusions still hold for other implementations.

Improved List Sphere Decoder for Multiple Antenna Systems

An improved list sphere decoder （ILSD） is proposed based on the conventional list sphere decoder （LSD） and the reduced- complexity maximum likelihood sphere-decoding algorithm. Unlike the conventional LSD with fixed initial radius, the ILSD adopts an adaptive radius to accelerate the list cdnstruction. Characterized by low-complexity and radius-insensitivity, the proposed algorithm makes iterative joint detection and decoding more realizable in multiple-antenna systems. Simulation results show that computational savings of ILSD over LSD are more apparent with more transmit antennas or larger constellations, and with no performance degradation. Because the complexity of the ILSD algorithm almost keeps invariant with the increasing of initial radius, the BER performance can be improved by selecting a sufficiently large radius.

Design and implementation of an efficient SDRAM controller for HDTV decoder

A high performance SDRAM controller for HDTV decoder is designed. MB-based （ macro block） address mapping, adaptive-precharge and command interleaving are adopted in this controller. MB-based address mapping reduces the precharge operations of the video processing unit in one access; adaptive- precharge avoids unnecessary precharge operations; while command interleaving inserts the precharge and activate commands of the next access into the command sequence of the current access, thus reduces the no operation （NOP） cycles. Combination of these three schemes effectively improves the SDRAM performance. Compared with precharge-all scheme, adaptive-precharge and command interleaving reduce the SDRAM overhead cycles by 70% and increases SDRAM performance by up to 19.2% in the best case. This controller has been implemented in an AVS SoC and the frequency is 200MHz.

Efficient VLSI architecture of CAVLC decoder with power optimized

This paper presents an efficient VLSI architecture of the contest-based adaptive variable length code （CAVLC） decoder with power optimized for the H.264/advanced video coding （AVC） standard. In the proposed design, according to the regularity of the codewords, the first one detector is used to solve the low efficiency and high power dissipation problem within the traditional method of table-searching. Considering the relevance of the data used in the process of runbefore＇s decoding, arithmetic operation is combined with finite state machine （FSM）, which achieves higher decoding efficiency. According to the CAVLC decoding flow, clock gating is employed in the module level and the register level respectively, which reduces 43% of the overall dynamic power dissipation. The proposed design can decode every syntax element in one clock cycle. When the proposed design is synthesized at the clock constraint of 100 MHz, the synthesis result shows that the design costs 11 300 gates under a 0.25 μm CMOS technology, which meets the demand of real time decoding in the H.264/AVC standard.

Low-loss belief propagation decoder with Tanner graph in quantum error-correction codes

Quantum error-correction codes are immeasurable resources for quantum computing and quantum communication.However,the existing decoders are generally incapable of checking node duplication of belief propagation(BP)on quantum low-density parity check(QLDPC)codes.Based on the probability theory in the machine learning,mathematical statistics and topological structure,a GF(4)(the Galois field is abbreviated as GF)augmented model BP decoder with Tanner graph is designed.The problem of repeated check nodes can be solved by this decoder.In simulation,when the random perturbation strength p=0.0115-0.0116 and number of attempts N=60-70,the highest decoding efficiency of the augmented model BP decoder is obtained,and the low-loss frame error rate(FER)decreases to 7.1975×10^(-5).Hence,we design a novel augmented model decoder to compare the relationship between GF(2)and GF(4)for quantum code[[450,200]]on the depolarization channel.It can be verified that the proposed decoder provides the widely application range,and the decoding performance is better in QLDPC codes.

利用Encoder-Decoder框架的深度学习网络实现绕射波分离及成像

利用单纯绕射波场实现地下地质异常体的识别具有坚实的理论基础,对应的实施方法得到了广泛研究,且有效地应用于实际勘探。但现有技术在微小尺度异常体成像方面收效甚微,相关研究多数以射线传播理论为基础,对于影响绕射波分离成像精度的因素分析并不完备。相较于反射波,由于存在不连续构造而产生的绕射波能量微弱并且相互干涉,同时环境干扰使得绕射波进一步湮没。因此,更高精度的波场分离及单独成像是现阶段基于绕射波超高分辨率处理、解释的重点研究方向。为此,首先针对地球物理勘探中地质异常体的准确定位,以携带高分辨率信息的绕射波为研究对象,系统分析在不同尺度、不同物性参数的异常体情况下绕射波的能量大小及形态特征,掌握绕射波与其他类型波叠加的具体形式;然后根据相应特征性质提出基于深度学习技术的绕射波分离成像方法,即利用Encoder-Decoder框架的空洞卷积网络捕获绕射波场特征,从而实现绕射波分离,基于速度连续性原则构建单纯绕射波场的偏移速度模型并完成最终成像。数据测试表明,该方法最终可满足微小地质异常体高精度识别的需求。

Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication

In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.