Parallel Implementation of the CCSDS Turbo Decoder on GPU

This paper presents a software turbo decoder on graphics processing units(GPU).Unlike previous works,the proposed decoding architecture for turbo codes mainly focuses on the Consultative Committee for Space Data Systems(CCSDS)standard.However,the information frame lengths of the CCSDS turbo codes are not suitable for flexible sub-frame parallelism design.To mitigate this issue,we propose a padding method that inserts several bits before the information frame header.To obtain low-latency performance and high resource utilization,two-level intra-frame parallelisms and an efficient data structure are considered.The presented Max-Log-Map decoder can be adopted to decode the Long Term Evolution(LTE)turbo codes with only small modifications.The proposed CCSDS turbo decoder at 10 iterations on NVIDIA RTX3070 achieves about 150 Mbps and 50Mbps throughputs for the code rates 1/6 and 1/2,respectively.

Iterative Decoding of Parallel Concatenated Block Codes and Coset Based MAP Decoding Algorithm for F24 Code

A multi dimensional concatenation scheme for block codes is introduced, in which information symbols are interleaved and re encoded for more than once. It provides a convenient platform to design high performance codes with flexible interleaver size. Coset based MAP soft in/soft out decoding algorithms are presented for the F24 code. Simulation results show that the proposed coding scheme can achieve high coding gain with flexible interleaver length and very low decoding complexity.

Cluster parallel rendering based on encoded mesh

Use of compressed mesh in parallel rendering architecture is still an unexplored area, the main challenge of which is to partition and sort the encoded mesh in compression-domain. This paper presents a mesh compression scheme PRMC (Parallel Rendering based Mesh Compression) supplying encoded meshes that can be partitioned and sorted in parallel rendering system even in encoded-domain. First, we segment the mesh into submeshes and clip the submeshes’ boundary into Runs, and then piecewise compress the submeshes and Runs respectively. With the help of several auxiliary index tables, compressed submeshes and Runs can serve as rendering primitives in parallel rendering system. Based on PRMC, we design and implement a parallel rendering architecture. Compared with uncompressed representation, experimental results showed that PRMC meshes applied in cluster parallel rendering system can dramatically reduce the communication requirement.

New Parallel Interference Cancellation for Convolutionally Coded CDMA Systems

Based on BCJR algorithm proposed by Bahlet al and linear soft decision feedback, a reduced-complexity parallel interference cancellation (simplified PIC) for convolutionally coded DS CDMA systems is proposed. By computer simulation, we compare the simplified PIC with the exact PIC. It shows that the simplified PIC can achieve the performance close to the exact PIC if the mean values of coded symbols are linearly computed in terms of the sum of initiala prior log-likelihood rate (LLR) and updateda prior LLR, while a significant performance loss will occur if the mean values of coded symbols are linearly computed in terms of the updateda prior LLR only. Meanwhile, we also compare the simplified PIC with MF receiver and conventional PICs. The simulation results show that the simplified PIC dominantly outperforms the MF receiver and conventional PICs, at signal-noise rate (SNR) of 7 dB, for example, the bit error rate is about 10?4 for the simplified PIC, which is far below that of matched-filter receiver and conventional PIC. Key words convolutionally coded CDMA - parallel interference cancellation - BCJR CLC number TN 914 Foundation item: Supported by the National Natural Science Foundation of China (69772015)Biography: Xu Guo-xiong (1967-), male, Ph. D candidate, research direction: wireless communication.

Parallelizing a Code for Counting and Computing Eigenvalues of Complex Tridiagonal Matrices and Roots of Complex Polynomials

A code developed recently by the authors, for counting and computing the eigenvalues of a complex tridiagonal matrix, as well as the roots of a complex polynomial, which lie in a given region of the complex plane, is modified to run in parallel on multi-core machines. A basic characteristic of this code (eventually pointing to its parallelization) is that it can proceed with: 1) partitioning the given region into an appropriate number of subregions;2) counting eigenvalues in each subregion;and 3) computing (already counted) eigenvalues in each subregion. Consequently, theoretically speaking, the whole code in itself parallelizes ideally. We carry out several numerical experiments with random complex tridiagonal matrices, and random complex polynomials as well, in order to study the behaviour of the parallel code, especially the degree of declination from theoretical expectations.

A reordered first fit algorithm based novel storage scheme for parallel turbo decoder

In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput （40-100 Mbps）, the hardware cost is still affordable for 3GPP＇s （3rd generation partnership project） interleaver.

A Novel Decoder Based on Parallel Genetic Algorithms for Linear Block Codes

Genetic algorithms offer very good performances for solving large optimization problems, especially in the domain of error-correcting codes. However, they have a major drawback related to the time complexity and memory occupation when running on a uniprocessor computer. This paper proposes a parallel decoder for linear block codes, using parallel genetic algorithms (PGA). The good performance and time complexity are confirmed by theoretical study and by simulations on BCH(63,30,14) codes over both AWGN and flat Rayleigh fading channels. The simulation results show that the coding gain between parallel and single genetic algorithm is about 0.7 dB at BER = 10﹣5 with only 4 processors.

Modified overlapped partly parallel decode for AR4JA codes in deep space communication

In this paper, according to the AR4JA codes in deep space communication, two kinds of iterative decoding including partly parallel decoding and overlapped partly parallel decoding are analyzed, and the advantages and disadvantages of them are listed. A modified overlapped partly parallel decoding that not only inherits the advantages of the two algorithms, but also overcomes the shortcomings of the two algorithms is proposed. The simulation results show that the three kinds of decoding have the same decoding performance; modified overlapped partly parallel decoding improves the iterative convergence rate and the throughput of system.

A parallel memory architecture for video coding

To efficiently exploit the performance of single instruction multiple data （SIMD） architectures for video coding, a parallel memory architecture with power-of-two memory modules is proposed. It employs two novel skewing schemes to provide conflict-free access to adjacent elements （8-bit and 16-bit data types） or with power-of-two intervals in both horizontal and vertical directions, which were not possible in previous parallel memory architectures. Area consumptions and delay estimations are given respectively with 4, 8 and 16 memory modules. Under a 0.18-pm CMOS technology, the synthesis results show that the proposed system can achieve 230 MHz clock frequency with 16 memory modules at the cost of 19k gates when read and write latencies are 3 and 2 clock cycles, respectively. We implement the proposed parallel memory architecture on a video signal processor （VSP）. The results show that VSP enhanced with the proposed architecture achieves 1.28× speedups for H.264 real-time decoding.

Particle flow code simulation of intact and fissured granitic rock samples

This study presents a calibration process of three-dimensional particle flow code(PFC3D)simulation of intact and fissured granite samples.First,laboratory stressestrain response from triaxial testing of intact and fissured granite samples is recalled.Then,PFC3D is introduced,with focus on the bonded particle models(BPM).After that,we present previous studies where intact rock is simulated by means of flatjoint approaches,and how improved accuracy was gained with the help of parametric studies.Then,models of the pre-fissured rock specimens were generated,including modeled fissures in the form of“smooth joint”type contacts.Finally,triaxial testing simulations of 1 t 2 and 2 t 3 jointed rock specimens were performed.Results show that both elastic behavior and the peak strength levels are closely matched,without any additional fine tuning of micro-mechanical parameters.Concerning the postfailure behavior,models reproduce the trends of decreasing dilation with increasing confinement and plasticity.However,the dilation values simulated are larger than those observed in practice.This is attributed to the difficulty in modeling some phenomena of fissured rock behaviors,such as rock piece corner crushing with dust production and interactions between newly formed shear bands or axial splitting cracks with pre-existing joints.

Impacts of optimization strategies on performance,power/energy consumption of a GPU based parallel reduction

In the era of modern high performance computing, GPUs have been considered an excellent accelerator for general purpose data-intensive parallel applications. To achieve application speedup from GPUs, many of performance-oriented optimization techniques have been proposed. However, in order to satisfy the recent trend of power and energy consumptions, power/energy-aware optimization of GPUs needs to be investigated with detailed analysis in addition to the performance-oriented optimization. In this work, in order to explore the impact of various optimization strategies on GPU performance, power and energy consumptions, we evaluate performance and power/energy consumption of a well-known application running on different commercial GPU devices with the different optimization strategies. In particular, in order to see the more generalized performance and power consumption patterns of GPU based accelerations, our evaluations are performed with three different Nvdia GPU generations(Fermi, Kepler and Maxwell architectures), various core clock frequencies and memory clock frequencies. We analyze how a GPU kernel execution is affected by optimization and what GPU architectural factors have much impact on its performance and power/energy consumption. This paper also categorizes which optimization technique primarily improves which metric(i.e., performance, power or energy efficiency). Furthermore, voltage frequency scaling(VFS) is also applied to examine the effect of changing a clock frequency on these metrics. In general, our work shows that effective GPU optimization strategies can improve the application performance significantly without increasing power and energy consumption.

Parallelization of intra prediction algorithm based on array processor

For the characteristics of intra prediction algorithms, the data dependence and parallelism between intra prediction models are first analyzed. This paper proposes a parallelization method based on dynamic reconfigurable array processors provided by the project team, and uses data level parallel(DLP) algorithms in multi-core units. The experimental results show that Y-component of peak signal to noise ratio(Y-PSNR) is improved about 10 dB and the time is saved 63% compared with high-efficiency video coding(HEVC) test model HM10.0. This method can effectively reduce codec time of the video and reduce computational complexity.

Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication

In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.

A simplified hardware-friendly contour prediction algorithm in 3D-HEVC and parallelization design

After the extension of depth modeling mode 4(DMM-4)in 3D high efficiency video coding(3D-HEVC),the computational complexity increases sharply,which causes the real-time performance of video coding to be impacted.To reduce the computational complexity of DMM-4,a simplified hardware-friendly contour prediction algorithm is proposed in this paper.Based on the similarity between texture and depth map,the proposed algorithm directly codes depth blocks to calculate edge regions to reduce the number of reference blocks.Through the verification of the test sequence on HTM16.1,the proposed algorithm coding time is reduced by 9.42%compared with the original algorithm.To avoid the time consuming of serial coding on HTM,a parallelization design of the proposed algorithm based on reconfigurable array processor(DPR-CODEC)is proposed.The parallelization design reduces the storage access time,configuration time and saves the storage cost.Verified with the Xilinx Virtex 6 FPGA,experimental results show that parallelization design is capable of processing HD 1080p at a speed above 30 frames per second.Compared with the related work,the scheme reduces the LUTs by 42.3%,the REG by 85.5%and the hardware resources by 66.7%.The data loading speedup ratio of parallel scheme can reach 3.4539.On average,the different sized templates serial/parallel speedup ratio of encoding time can reach 2.446.

Turbo Decoding中BCJR算法的应用及改进

并行级连卷积码 (Turbo Codes)是近年来在编码理论上的一个重大突破 ,其性能与信道容量极限的差距可小于 1d B,有着极其广阔的应用前景 ,而其独特的迭代译码方法更成了编码界和通信界讨论的热点。讨论了 Turbo Codes的编译码原理及 BCJR算法 ,比较了 SOVA,M- BCJR及T- BJCR等几种简化译码算法的性能 ,并对后两者的工程应用进行了探讨。

CCOC：An Optimizing Compiling System for Concurrent C Supporting Inter－process Code Analysis and Optimization

At present, there are some static code analyses and optimizations that can be applied to Concurrent C programs to improve their performance or verify their logical correctness. These analyses and optimizations are inter-process. In order to make their implementation easy, we propose a new method to construct an optimizing compiling system CCOC for Concurrent C. CCOC supports inter-process code analysis and optimization to Concurrent C programs and does not affect the system's portability and separate compilation of source programs. We also discuss some implementation details of CCOC briefly.

PIC-MF-based Iterative Receiver for Multiuser Space Frequency Block Coding Systems

A novel low-complexity iterative receiver for multiuser space frequency block coding (SFBC) system was proposed in this paper. Unlike the conventional linear minimum mean square error (MMSE) detector, which requires matrix inversion at each iteration, the soft-in soft-out (SISO) detector is simply a parallel interference cancellation (PIC)-matched filter (MF) operation. The probability density function (PDF) of PIC-MF detector output is approximated as Gaussian, whose variance is calculated with a priori information fed back from the channel decoder. With this approximation, the log likelihood ratios (LLRs) of transmitted bits are under-estimated. Then the LLRs are multiplied by a constant factor to achieve a performance gain. The constant factor is optimized according to extrinsic information transfer (EXIT) chart of the SISO detector. Simulation results show that the proposed iterative receiver can significantly improve the system performance and converge to the matched filter bound (MFB) with low computational complexity at high signal-to-noise ratios (SNRs).

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

APPLICATION OF TURBO CODES IN HIGH-SPEED REAL-TIME CHANNEL

The time delay of Turbo codes due to its iterative decoding is the main bottleneck of its application in real-time channel. However, the time delay can be greatly shortened through the adoption of parallel decod-ing algorithm, dividing the received bits into several sub-blocks and processing in parallel. This letter mainly discusses the applicability of turbo codes in high-speed real-time channel through the study of a parallel turbo decoding algorithm based on 3GPP-proposed turbo encoder and interleaver in various channel. Simulation re-sult shows that, by choosing an appropriate sub-block length, the time delay can be obviously shortened with-out degrading the performance and increasing hardware complexity, and furthermore indicates the applicability of Turbo codes in high-speed real-time channel.

Turbo Coded OFDM with Large Number of Subcarriers

Wireless communication systems have greatly advanced during the last years. A significant contributor in these systems’ performance has been Orthogonal Frequency Division Multiplexing (OFDM). Since its invention, it is considered to be a technological leap. This leap in splitting an information stream in multiple frequency carriers has been adapted by various scientists working on the development of wireless systems. Moreover, as OFDM presented excellent tolerance of channel fading and noise signals, the evolvement in terms of speed and reliability was consequent, because only a small stream of information is lost due to noise effects. OFDM along with the knowledge that Turbo codes is another excellent scheme of reducing BER, has triggered us to expand our research. So, we experimented in simulation level not only in joining OFDM with Turbo Codes but even in finding a better Turbo scheme compared to a typical PCCC, SCCC and a Convolutional encoder with Viterbi decoder. As the last goal has already been accomplished, in this paper is presented the new OFDM system consisted of our Turbo scheme. The analysis of the previous system took into consideration the effects of an AWGN channel. Also, this noise analysis was conducted using a simulation platform with specific attributes such as transmitting and receiving fixed number of subcarriers (2048 carriers after IFFT block) while using different types of convolutional concatenated codes, such as PCCC (Parallel), SCCC (Serial) and the new PCCC scheme. The results clearly show not only the improvement in the BER performance of the Turbo Coded OFDM systems (compared to others consisted of Viterbi decoders) but the overall superiority of the proposed design.