A novel inverter power source is developed characterized with constant output current and unit power factor input. Digital signal processor （ DSP ） is used to realize power factor correction and control of back-stag...A novel inverter power source is developed characterized with constant output current and unit power factor input. Digital signal processor （ DSP ） is used to realize power factor correction and control of back-stage inverter bridge of the arc welding inverter. The fore-stage adopts double closed loop proportion and integration （PI） rectifier technique and the back- stage adopts digital pulse width modulation （ PWM） technique. Simulated waves can be obtained in Matlab/Simulink and validated by experiments. Experiments of the prototype showed that the total harmonic distortion （THD） can be controlled within 10% and the power factor is approximate to 1.展开更多
A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gatin...A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.展开更多
With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption ...With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption of the 16-bit datapath in a 32-bit reconfigurable pipelined Digital Signal Processor (DSP) is introduced. By keeping the old input values and preventing the useless switching of the logic blocks on the datapath, the power consumption is much lowered. At the same time, by relocating some logic blocks between different pipeline stages and employing some data forward logics, a better balanced pipeline is achieved to lower the power consumption for conditional computation instructions at very low timing and area costs. The effectivity of these power optimization technologies are proved by the experimental results. Finally, some ideas about how to reduce the power consumption of circuits are proposed, which are very effective and useful in practice designs, especially in pipelined ones.展开更多
Spurious signals in direct digital frequency synthesizers （DDFSs） are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These si...Spurious signals in direct digital frequency synthesizers （DDFSs） are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These signals are deterministic and periodic in the time domain, so they appear as line spectra in the frequency domain. Two types of spurious signals due to amplitude quantization are exactly formulated and compared in the time and frequency domains respectively. Then the frequency spectra and power levels of the spurious signals due to amplitude quantization in the absence of phase-accumulator truncation are emphatically analyzed, and the effects of the DDFS parameter variations on the spurious signals are thoroughly studied by computer simulation. And several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.展开更多
The growing problems of harmonic pollution on coal mine power lines caused by high-power DC drive systems has increased the use of active power filters.We analyzed compensation errors caused by the time lag in the det...The growing problems of harmonic pollution on coal mine power lines caused by high-power DC drive systems has increased the use of active power filters.We analyzed compensation errors caused by the time lag in the detecting circuits of an active power filter based on DSP control.We derived a mathematical model for the compensation error starting from the error estimation when a single distortion frequency is present.This model was then extended to the case where multiple frequencies are present in the distortion.A formula for a general theory of compensation error with fixed load and fixed lag time is presented.The theoretical analysis and experimental results show that the delay time of an active power filter mainly arises from the sampling time.Lower sampling frequencies introduce larger compensation errors in the active power filter reference current.展开更多
This letter studies and analyzes the working features of main circuit of tri-level boost Power Factor Correct(PFC) converter and the advantages of tri-level switch converter in aspects of bearing high-voltage of power...This letter studies and analyzes the working features of main circuit of tri-level boost Power Factor Correct(PFC) converter and the advantages of tri-level switch converter in aspects of bearing high-voltage of power components,overall system loss and magnetic component selection based upon the single-level boost PFC switch converter.Besides,relying on the application of mi-croprocessor in power converter technology and DSP(Digital Signal Processing) chip's strong cal-culating capacity,the letter presents the adoption of modified scheme of tri-level boost PFC converter under the control of predictive control algorithm.Moreover,the operating principle and control method are specified,the results of circuit test and analysis are provided and the advantages of pre-dictive control technology-based multi-level boost PFC converter is verified.展开更多
This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimizati...This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.展开更多
A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very la...A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.展开更多
This paper presents a real-time power flow controller for VSIs （voltage source inverters） interfaced to low voltage microgrids. The proposed controller is modular, flexible, intelligent, inexpensive, portable, adapt...This paper presents a real-time power flow controller for VSIs （voltage source inverters） interfaced to low voltage microgrids. The proposed controller is modular, flexible, intelligent, inexpensive, portable, adaptive and designed to positively contribute in low voltage microgrids in which the lines R/X ratio is greater than the transmission lines. Therefore, the proposed control strategy is developed for operation in distribution lines. The controller strategy is different from the conventional grid-connected inverters which are designed based on transmission line characteristics. This controller, using a Texas Instrument general purpose DSP （digital signal processor）, is programmed and tuned using MATLAB/SIMULINK in order to enhance self-healing, reliability and stability of the grid. This general purpose controller makes proper decisions using its local measurements as the primary source of data. The controller has the capability of communicating with the adjacent controllers and sharing the information if/when needed. The power flow output of the inverter is tested for both islanded and grid-connected modes of operation. The inverter positively contributes to active and reactive power supply while operating in grid-connected mode. The proposed control method has been implemented on a Texas Instrument DSC （digital signal controller） chip and tested on a hardware test bench at the Alternative Energy Laboratory at WVU1T （West Virginia University Institute of Technology）. The system＇s experimental results veri~ the validity and efficiency of the proposed controller.展开更多
The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The pr...The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The proposed low-cost approach has been applied and validated by the implementation of an industrial regulator in a real time hardware-in-the-loop simulation of a mixed islanded power network including precise models of the hydraulic system. The studied network is constituted of three different types of electrical power generation systems and a consumer.展开更多
文摘A novel inverter power source is developed characterized with constant output current and unit power factor input. Digital signal processor （ DSP ） is used to realize power factor correction and control of back-stage inverter bridge of the arc welding inverter. The fore-stage adopts double closed loop proportion and integration （PI） rectifier technique and the back- stage adopts digital pulse width modulation （ PWM） technique. Simulated waves can be obtained in Matlab/Simulink and validated by experiments. Experiments of the prototype showed that the total harmonic distortion （THD） can be controlled within 10% and the power factor is approximate to 1.
基金The Research Project of China Military Department (No6130325)
文摘A novel clock structure of a low-power 16-bit very large instruction word (VLIW) digital signal processor (DSP) was proposed. To improve deterministic clock gating and to solve the drawback of conventional clock gating circuit in high speed circuit, a distributed and early clock gating method was developed on its instruction fetch & decoder unit, its pipelined data-path unit and its super-Harvard memory interface unit. The core was implemented following the Synopsys back-end flow under TSMC (Taiwan Silicon manufacture corporation) 0.18-μm 1.8-V 1P6M process, with a core size of 2 mm×2 mm. Result shows that it can run under 200 MHz with a power performance around 0.3 mW/MIPS. Meanwhile, only 39.7% circuit is active simultaneously in average, compared to its non-gating counterparts.
文摘With the continuous increasing of circuit scale, the problem of power consumption is paid much more attention than before, especially in large designs. In this paper, an experience of optimizing the power consumption of the 16-bit datapath in a 32-bit reconfigurable pipelined Digital Signal Processor (DSP) is introduced. By keeping the old input values and preventing the useless switching of the logic blocks on the datapath, the power consumption is much lowered. At the same time, by relocating some logic blocks between different pipeline stages and employing some data forward logics, a better balanced pipeline is achieved to lower the power consumption for conditional computation instructions at very low timing and area costs. The effectivity of these power optimization technologies are proved by the experimental results. Finally, some ideas about how to reduce the power consumption of circuits are proposed, which are very effective and useful in practice designs, especially in pipelined ones.
基金supported by the National Grand Fundamental Research 973 Program of China(2004CB318109)the National High Technology Research and Development Program of China(863 Program)(2006AA01Z452).
文摘Spurious signals in direct digital frequency synthesizers （DDFSs） are partly caused by amplitude quantization and phase truncation, which affect their application to many wireless telecommunication systems. These signals are deterministic and periodic in the time domain, so they appear as line spectra in the frequency domain. Two types of spurious signals due to amplitude quantization are exactly formulated and compared in the time and frequency domains respectively. Then the frequency spectra and power levels of the spurious signals due to amplitude quantization in the absence of phase-accumulator truncation are emphatically analyzed, and the effects of the DDFS parameter variations on the spurious signals are thoroughly studied by computer simulation. And several important conclusions are derived which can provide theoretical support for parameter choice and spurious performance evaluation in the application of DDFSs.
基金provided by the National Basic Research Program of China (No.2005CB221505)
文摘The growing problems of harmonic pollution on coal mine power lines caused by high-power DC drive systems has increased the use of active power filters.We analyzed compensation errors caused by the time lag in the detecting circuits of an active power filter based on DSP control.We derived a mathematical model for the compensation error starting from the error estimation when a single distortion frequency is present.This model was then extended to the case where multiple frequencies are present in the distortion.A formula for a general theory of compensation error with fixed load and fixed lag time is presented.The theoretical analysis and experimental results show that the delay time of an active power filter mainly arises from the sampling time.Lower sampling frequencies introduce larger compensation errors in the active power filter reference current.
文摘This letter studies and analyzes the working features of main circuit of tri-level boost Power Factor Correct(PFC) converter and the advantages of tri-level switch converter in aspects of bearing high-voltage of power components,overall system loss and magnetic component selection based upon the single-level boost PFC switch converter.Besides,relying on the application of mi-croprocessor in power converter technology and DSP(Digital Signal Processing) chip's strong cal-culating capacity,the letter presents the adoption of modified scheme of tri-level boost PFC converter under the control of predictive control algorithm.Moreover,the operating principle and control method are specified,the results of circuit test and analysis are provided and the advantages of pre-dictive control technology-based multi-level boost PFC converter is verified.
基金Supported by the National Natural Science Foundation of China (No. 60475018)
文摘This paper presents the design and implementation of a low power digital signal processor （THUCIDSP-1 ） targeting at application for cochlear implants. Multi-level low power strategies including algorithm optimization, operand isolation, clock gating and memory partitioning are adopted in the processor design to reduce the power consumption. Experimental results show that the complexity of the Continuous Interleaved Sampling （CIS） algorithm is reduced by more than 80 % and the power dissipation of the hardware alone is reduced by about 25% with the low power methods. The THUCIDSP-1 prototype, fabricated in 0.18-μm standard CMOS process, consumes only 1.91 mW when executing the CIS algorithm at 3 MHz.
基金supported by the National Natural Science Foundation of China under Grant No.90407007University Science Foundation of China under Grant No R0820207
文摘A kind of pseudo Gray code presentation of test patterns based on accumulation generators is presented and a low power test scheme is proposed to test computational function modules with contiguous subspace in very large scale integration （VLSI）, especially in digital signal processors （DSP）. If test patterns from accumulators for the modules are encoded in the pseudo Gray code presentation, the switching activities of the modules are reduced, and the decrease of the test power consumption is resulted in. Results of experimentation based on FPGA show that the test approach can reduce dynamic power consumption by an average of 17.40% for 8-bit ripple carry adder consisting of 3-2 counters. Then implementation of the low power test in hardware is exploited. Because of the reuse of adders, introduction of additional XOR logic gates is avoided successfully. The design minimizes additional hardware overhead for test and needs no adjustment of circuit structure. The low power test can detect any combinational stuck-at fault within the basic building block without any degradation of original circuit performance.
文摘This paper presents a real-time power flow controller for VSIs （voltage source inverters） interfaced to low voltage microgrids. The proposed controller is modular, flexible, intelligent, inexpensive, portable, adaptive and designed to positively contribute in low voltage microgrids in which the lines R/X ratio is greater than the transmission lines. Therefore, the proposed control strategy is developed for operation in distribution lines. The controller strategy is different from the conventional grid-connected inverters which are designed based on transmission line characteristics. This controller, using a Texas Instrument general purpose DSP （digital signal processor）, is programmed and tuned using MATLAB/SIMULINK in order to enhance self-healing, reliability and stability of the grid. This general purpose controller makes proper decisions using its local measurements as the primary source of data. The controller has the capability of communicating with the adjacent controllers and sharing the information if/when needed. The power flow output of the inverter is tested for both islanded and grid-connected modes of operation. The inverter positively contributes to active and reactive power supply while operating in grid-connected mode. The proposed control method has been implemented on a Texas Instrument DSC （digital signal controller） chip and tested on a hardware test bench at the Alternative Energy Laboratory at WVU1T （West Virginia University Institute of Technology）. The system＇s experimental results veri~ the validity and efficiency of the proposed controller.
文摘The present paper deals with the development of a modular, flexible and structured block to block approach for the study of regulators by implementing the different blocks on a DSP （digital signal processor）. The proposed low-cost approach has been applied and validated by the implementation of an industrial regulator in a real time hardware-in-the-loop simulation of a mixed islanded power network including precise models of the hydraulic system. The studied network is constituted of three different types of electrical power generation systems and a consumer.
