Lowering the Error Floor of ADMM Penalized Decoder for LDPC Codes

Decoding by alternating direction method of multipliers(ADMM) is a promising linear programming decoder for low-density parity-check(LDPC) codes. In this paper, we propose a two-step scheme to lower the error floor of LDPC codes with ADMM penalized decoder.For the undetected errors that cannot be avoided at the decoder side, we modify the code structure slightly to eliminate low-weight code words. For the detected errors induced by small error-prone structures, we propose a post-processing method for the ADMM penalized decoder. Simulation results show that the error floor can be reduced significantly over three illustrated LDPC codes by the proposed two-step scheme.

Construction of Protograph LDPC Codes Based on the Convolution Neural Network

This paper presents an intelligent protograph construction algorithm.Protograph LDPC codes have shown excellent error correction performance and play an important role in wireless communications.Random search or manual construction are often used to obtain a good protograph,but the efficiency is not high enough and many experience and skills are needed.In this paper,a fast searching algorithm is proposed using the convolution neural network to predict the iterative decoding thresholds of protograph LDPC codes effectively.A special input data transformation rule is applied to provide stronger generalization ability.The proposed algorithm converges faster than other algorithms.The iterative decoding threshold of the constructed protograph surpasses greedy algorithm and random search by about 0.53 dB and 0.93 dB respectively under 100 times of density evolution.Simulation results show that quasi-cyclic LDPC(QC-LDPC)codes constructed from the proposed algorithm have competitive performance compared to other papers.

Weighted symbol-flipping decoding algorithm for nonbinary LDPC codes with flipping patterns

A novel low-complexity weighted symbol-flipping algorithm with flipping patterns to decode nonbinary low-density parity-check codes is proposed. The proposed decoding procedure updates the hard-decision received symbol vector iteratively in search of a valid codeword in the symbol vector space. Only one symbol is flipped in each iteration, and symbol flipping function, which is employed as the symbol flipping metric, combines the number of failed checks and the reliabilities of the received bits and calculated symbols. A scheme to avoid infinite loops and select one symbol to flip in high order Galois field search is also proposed. The design of flipping pattern＇s order and depth, which is dependent of the computational requirement and error performance, is also proposed and exemplified. Simulation results show that the algorithm achieves an appealing tradeoff between performance and computational requirement over relatively low Galois field for short to medium code length.

Real-Time Implementation for Reduced-Complexity LDPC Decoder in Satellite Communication

In this paper,it has proposed a realtime implementation of low-density paritycheck(LDPC) decoder with less complexity used for satellite communication on FPGA platform.By adopting a(2048.4096)irregular quasi-cyclic(QC) LDPC code,the proposed partly parallel decoding structure balances the complexity between the check node unit(CNU) and the variable node unit(VNU) based on min-sum(MS) algorithm,thereby achieving less Slice resources and superior clock performance.Moreover,as a lookup table(LUT) is utilized in this paper to search the node message stored in timeshare memory unit,it is simple to reuse and save large amount of storage resources.The implementation results on Xilinx FPGA chip illustrate that,compared with conventional structure,the proposed scheme can achieve at last 28.6%and 8%cost reduction in RAM and Slice respectively.The clock frequency is also increased to 280 MHz without decoding performance deterioration and convergence speed reduction.

Construction of LDPC Codes for the Layered Decoding Algorithm

The layered decoding algorithm has been widely used in the implementation of Low Density Parity Check (LDPC) decoders, due to its high convergence speed. However, the pipeline operation of the layered decoder may introduce memory access conflicts, which heavily deteriorates the decoder throughput. To essentially deal with the issue of memory access conflicts, we propose a construction algorithm of LDPC codes, to which a constraint condition is added in the Progressive Edge-Growth (PEG) algorithm. The constraint condition can guarantee that for our constructed LDPC codes, the sets of all the variable nodes connected to the consecutive layers do not share any common variable node, which can avoid the memory access conflicts. Simulation results show that the performance of our constructed LDPC codes is close to the several other LDPC codes adopted in wireless standards. Moreover, compared with the decoder for IEEE 802. 16e LDPC codes, the throughput of our LDPC decoder has large improvement, while the chip resource consumption is unchanged. Thus, our constructed LDPC codes can be adopted in the high-speed transmission.

JOINT SOURCE-CHANNEL DECODING OF HUFFMAN CODES WITH LDPC CODES

In this paper, we present a Joint Source-Channel Decoding algorithm (JSCD) for Low-Density Parity Check (LDPC) codes by modifying the Sum-Product Algorithm (SPA) to account for the source redun-dancy, which results from the neighbouring Huffman coded bits. Simulations demonstrate that in the presence of source redundancy, the proposed algorithm gives better performance than the Separate Source and Channel Decoding algorithm (SSCD).

Serial Genetic Algorithm Decoder for Low Density Parity Check Codes

Genetic algorithms are successfully used for decoding some classes of error correcting codes, and offer very good performances for solving large optimization problems. This article proposes a new decoder based on Serial Genetic Algorithm Decoder (SGAD) for decoding Low Density Parity Check (LDPC) codes. The results show that the proposed algorithm gives large gains over sum-product decoder, which proves its efficiency.

Research of Multi-Rate LDPC Decoding in Optical Communication System

Low-density parity-check code (LDPC) not only has good performance approaching the Shannon limit, but also has low decoding complexity and flexible structure. It is a research hot-spot in the field of channel coding in recent years and has a wide range of application prospects in optical communication systems. In this paper, the decoding aspects and performance of LDPC codes are analyzed and compared according to the bit error rate (BER) of LDPC codes. The computer simulation was carried out under additive white Gaussian noise (AWGN) channel and binary phase shift keying (BPSK) modulation. Through theoretical analysis and simulation results, this paper explores the way of multi-rate LDPC decoding.

Hybrid weighted symbol-flipping decoding for nonbinary LDPC codes

A hybrid decoding algorithm is proposed for nonbinary low-density parity-check(LDPC)codes,which combines the weighted symbol-flipping(WSF)algorithm with the fast Fourier transform q-ary sum-product algorithm(FFT-QSPA).The flipped position and value are determined by the symbol flipping metric and the received bit values in the first stage WSF algorithm.If the lowcomplexity WSF algorithm is failed,the second stage FFT-QSPA is activated as a switching strategy.Simulation results show that the proposed hybrid algorithm greatly reduces the computational complexity with the performance close to that of FFT-QSPA.

基于可靠度差值特征的自适应判决多元LDPC译码算法

利用变量节点符号可靠度在迭代过程中的分布特征,提出了一种基于可靠度差值特征的自适应判决多元低密度奇偶校验(Low Density Parity Check, LDPC)译码算法。整个迭代过程划分为两个阶段,针对不同阶段节点可靠度的差值特征分别采用不同的判决策略:前期阶段,采用传统的基于最大可靠度的判决策略;后期阶段,根据最大、次大可靠度之间的差值特征,设计自适应的码元符号判决策略。仿真结果表明,所提算法在相当的译码复杂度前提下,能获得0.15~0.4 dB的性能增益。同时,对于列重较小的LDPC码,具有更低的译码错误平层。

基于分层最小和译码的RS-LDPC级联码改进算法

RS-LDPC级联码能够有效提高数据传输的可靠性和系统的容错能力,在5G通信等领域中得到了广泛的应用,且在6G中具有很好的应用前景。但是RS-LDPC级联码与单码相比具有计算复杂度高、不易于在硬件上实现的不足,因此提出一种基于分层最小和的RS-LDPC级联码改进译码算法,将LDPC码的校验矩阵分解成多个子矩阵,在不同子矩阵层次上并行计算。此外,还引入了新的关于校验节点信息更新的简化函数,旨在保证译码性能的同时降低计算复杂度,达到易于硬件实现的目的。结果表明改进型分层最小和算法复杂度大大降低,且在性能上优于传统BP译码0.25 dB左右。

A Decode-and-Forward Scheme for LDPC Coded Three-Way Relay Fading Channels

In this paper a low-density pairwise check(LDPC) coded three-way relay system is considered, where three user nodes desire to exchange messages with the help of one relay node. Since physical-layer network coding is applied, two time slots are sufficient for one round information exchange. In this paper, we present a decode-and-forward(DF) scheme based on joint LDPC decoding for three-way relay channels, where relay decoder partially decodes the network code rather than fully decodes all the user messages. Simulation results show that the new DF scheme considerably outperforms other common schemes in three-way relay fading channels.

Construction of Short-Block Nonbinary LDPC Codes Based on Cyclic Codes

In this paper, we focus on shortblock nonbinary LDPC(NB-LDPC) codes based on cyclic codes. Based on Tanner graphs' isomorphism, we present an efficient search algorithm for finding non-isomorphic binary cyclic LDPC codes. Notice that the parity-check matrix H of the resulting code is square and not of full rank, and its row weight and column weight are the same. By replacing the ones in the same column of H with a nonzero element of fi nite fi elds GF(q), a class of NB-LDPC codes over GF(q) is obtained. Numerical results show that the constructed codes perform well over the AWGN channel and have fast decoding convergence. Therefore, the proposed NB-LDPC codes provide a promising coding scheme for low-latency and high-reliability communications.

Low-Complexity Detection and Decoding Scheme for LDPC-Coded MLC NAND Flash Memory

With the development of manufacture technology, the multi-level cell(MLC)technique dramatically increases the storage density of NAND flash memory. As the result,cell-to-cell interference(CCI) becomes more serious and hence causes an increase in the raw bit error rate of data stored in the cells.Recently, low-density parity-check(LDPC)codes have appeared to be a promising solution to combat the interference of MLC NAND flash memory. However, the decoding complexity of the sum-product algorithm(SPA) is extremely high. In this paper, to improve the accuracy of the log likelihood ratio(LLR) information of each bit in each NAND flash memory cell, we adopt a non-uniform detection(N-UD) which uses the average maximum mutual information to determine the value of the soft-decision reference voltages.Furthermore, with an aim to reduce the decoding complexity and improve the decoding performance, we propose a modified soft reliabilitybased iterative majority-logic decoding(MSRBI-MLGD) algorithm, which uses a non-uniform quantizer based on power function to decode LDPC codes. Simulation results show that our design can offer a desirable trade-off between the performance and complexity for high-column-weight LDPC-coded MLC NAND flash memory.

空间耦合量子LDPC码的双窗口滑动译码

量子纠错码是应对量子计算过程中不可避免的噪声干扰的关键途径。和其经典情形一样,空间耦合量子LDPC码理论上也可在纠错性能和译码时延间取得良好的均衡。考虑到目前采用常规置信传播算法(BPA)的空间耦合量子LDPC(SC-QLDPC)码在译码过程中仍存在复杂度高和译码时延长的问题,受经典滑窗译码算法的启发,并结合和利用SC-QLDPC码所对应的两个奇偶校验矩阵在主对角线和副对角线上具有非零对角带的结构特点,提出了针对量子SC-QLDPC码的滑窗译码算法(称为量子双窗口滑动译码算法)。在该策略中,通过窗口在两个经典校验矩阵主副对角线上的同时滑动,保证了相应量子比特部分译码所需的相位与比特翻转错误图样信息的提取,从而使其在译码性能和时延之间取得良好均衡。对所提量子双窗口滑动译码算法进行仿真验证,结果表明其不仅能提供灵活的低时延译码输出,并且当窗口扩大时,其译码性能逼近标准的量子置信传播算法,显著提升了SC-QLDPC码的应用范围。

Joint Iterative Decoding for Network-Coding-Based Multisource LDPC-Coded Cooperative MIMO

A network-coding-based multisource LDPC-coded cooperative MIMO scheme is proposed,where multiple sources transmit their messages to the destination with the assistance from a single relay.The relay cooperates with multiple sources simultaneously via network-coding.It avoids the issues of imperfect frequency/timing synchronization and large transmission delay which may be introduced by frequency-division multiple access(FDMA)/code-division multiple access(CDMA)and time-division multiple access(TDMA)manners.The proposed joint″Min-Sum″iterative decoding is effectively carried out in the destination.Such a decoding algorithm agrees with the introduced equivalent joint Tanner graph which can be used to fully characterize LDPC codes employed by the sources and relay.Theoretical analysis and numerical simulation show that the proposed scheme with joint iterative decoding can achieve significant cooperation diversity gain.Furthermore,for the relay,compared with the cascade scheme,the proposed scheme has much lower complexity of LDPC-encoding and is easier to be implemented in the hardware with similar bit error rate(BER)performance.

Design of bilayer lengthened LDPC codes over expanded graph for relay channels

This paper presents a low complexity optimized algorithm for design of bilayer lengthened LDPC(BL-LDPC) code for decode-and-forward relay system.The design is performed over the expanded graph of the BL-LDPC code,which consists of the original bilayer graph and the extra added relaygenerated parity check bits.To build up our proposed optimized algorithm,we present a modified Gaussian approximation algorithm for the expanded structure of the BL-LDPC code.Then using the proposed optimized algorithm,we find the optimum overall expanded graph of the BL-LDPC code.Simulation results show that the BL-LDPC codes obtained by our proposed optimized algorithm have excellent bit-error-rate performances and small gaps between the convergence thresholds and the theoretical limits when transmitted over the additive white Gaussian noise channels.

HIGH-PERFORMANCE SIMPLE-ENCODING GENERATOR-BASED SYSTEMATIC IRREGULAR LDPC CODES AND RESULTED PRODUCT CODES

Low-Density Parity-Check (LDPC) code is one of the most exciting topics among the coding theory community.It is of great importance in both theory and practical communications over noisy channels.The most advantage of LDPC codes is their relatively lower decoding complexity compared with turbo codes,while the disadvantage is its higher encoding complexity.In this paper,a new ap- proach is first proposed to construct high performance irregular systematic LDPC codes based on sparse generator matrix,which can significantly reduce the encoding complexity under the same de- coding complexity as that of regular or irregular LDPC codes defined by traditional sparse parity-check matrix.Then,the proposed generator-based systematic irregular LDPC codes are adopted as con- stituent block codes in rows and columns to design a new kind of product codes family,which also can be interpreted as irregular LDPC codes characterized by graph and thus decoded iteratively.Finally, the performance of the generator-based LDPC codes and the resultant product codes is investigated over an Additive White Gaussian Noise (AWGN) and also compared with the conventional LDPC codes under the same conditions of decoding complexity and channel noise.

AN ITERATIVE RELIABILITY-BASED DECODING FOR LDPC CODED MODULATION SYSTEM

In this paper, A Belief Propagation concatenated Orderd-Statistic Decoder (BP-OSD) based on accumulated Log-Likelihood Ratio (LLR) is proposed for medium and short lengths Low Density Parity-Check (LDPC) codes coded Bit-Interleaved Coded Modulation (BICM) systems. The accumulated soft output values delivered by every BP iteration are used as reliability values of Soft-Input Soft-Output OSD (SISO-OSD) decoder and the soft output of SISO-OSD is used as a priori probabilities of the demodulator for the next iteration. Simulation results show that this improved algorithm achieves noticeable performance gain with only modest increase in computation complexity.