A review on the design of ternary logic circuits

A multi-valued logic system is a promising alternative to traditional binary logic because it can reduce the complexity,power consumption, and area of circuit implementation. This article briefly summarizes the development of ternary logic and its advantages in digital logic circuits. The schemes, characteristics, and application of ternary logic circuits based on CMOS, CNTFET, memristor, and other devices and processes are reviewed in this paper, providing some reference for the further research and development of ternary logic circuits.

DESIGN OF TWO-PHASE SINUSOIDAL POWER CLOCK AND CLOCKED TRANSMISSION GATE ADIABATIC LOGIC CIRCUIT

First the research is conducted on the design of the two-phase sinusoidal power clock generator in this paper. Then the design of the new adiabatic logic circuit adopting the two-phase sinusoidal power clocks--Clocked Transmission Gate Adiabatic Logic （CTGAL） circuit is presented. This circuit makes use of the clocked transmission gates to sample the input signals, then the output loads are charged and discharged in a fully adiabatic manner by using bootstrapped N-Channel Metal Oxide Semiconductor （NMOS） and Complementary Metal Oxide Semiconductor （CMOS） latch structure. Finally, with the parameters of Taiwan Semiconductor Manufacturing Company （TSMC） 0.25um CMOS device, the transient energy consumption of CTGAL, Bootstrap Charge-Recovery Logic （BCRL） and Pass-transistor Adiabatic Logic （PAL） including their clock generators is simulated. The simulation result indicates that CTGAL circuit has the characteristic of remarkably low energy consumption.

A UNIFIED THEORY FOR DESIGNING ANDANALYZING BOTH SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

The paper discusses general expressions of the clock signal and the next state equations containing the clock signal for flip-flops, and based on it, a unified theory for designing and analyzing both synchronous and asynchronous sequential circuits is proposed. The theory is proved effective by practical examples.

Two Analytical Methods for Detection and Elimination of the Static Hazard in Combinational Logic Circuits

In this paper, the authors continue the researches described in [1], that consists in a comparative study of two methods to eliminate the static hazard from logical functions, by using the form of Product of Sums (POS), static hazard “0”. In the first method, it used the consensus theorem to determine the cover term that is equal with the product of the two residual implicants, and in the second method it resolved a Boolean equation system. The authors observed that in the second method the digital hazard can be earlier detected. If the Boolean equation system is incompatible (doesn’t have solutions), the considered logical function doesn’t have the static 1 hazard regarding the coupled variable. Using the logical computations, this method permits to determine the needed transitions to eliminate the digital hazard.

High performance integrated photonic circuit based on inverse design method

The basic indexes of all-optical integrated photonic circuits include high-density integration,ultrafast response and ultralow energy consumption.Traditional methods mainly adopt conventional micro/nano-structures.The overall size of the circuit is large,usually reaches hundreds of microns.Besides,it is difficult to balance the ultrafast response and ultra-low energy consumption problem,and the crosstalk between two traditional devices is difficult to overcome.Here,we propose and experimentally demonstrate an approach based on inverse design method to realize a high-density,ultrafast and ultra-low energy consumption integrated photonic circuit with two all-optical switches controlling the input states of an all-optical XOR logic gate.The feature size of the whole circuit is only 2.5μm×7μm,and that of a single device is 2μm×2μm.The distance between two adjacent devices is as small as 1.5μm,within wavelength magnitude scale.Theoretical response time of the circuit is 150 fs,and the threshold energy is within 10 fJ/bit.We have also considered the crosstalk problem.The circuit also realizes a function of identifying two-digit logic signal results.Our work provides a new idea for the design of ultrafast,ultra-low energy consumption all-optical devices and the implementation of high-density photonic integrated circuits.

Design Technique of I^2L Circuits Based on Multi-Valued Logic

This paper proposes the use of the current signal to express logic values and establishes the theory of grounded current switches suitable for I2L circuits.Based on the advantage that current signals are easy to be added, the design technique of I2L circuits by means of the multi-valued current signal is proposed.It is shown that simpler structure of I2L circuits can be obtained with this technique.

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

The physical limitations of complementary metal-oxide semiconductor?(CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.

SYNCHRONOUS DERIVED CLOCK AND SYNTHESIS OF LOW POWER SEQUENTIAL CIRCUITS

Based on analyzing significance of controlling clock in design of low power sequential circuits, this paper proposes a technique that the gating signal is derived from the master latch in a flip-flop to make the derived clock having no glitch and no skew. The design of a decimal counter with half-frequency division shows that by using the synchronous derived clock the counter has lower power dissipation as well as simpler combinational logic. Computer simulation shows 20% power saving.

CircuitVerse:A Simulator for Teaching and Learning of Digital Logic Circuit

Digital Logic is a fundamental course of majors in electronic information.The simulation experiment is an essential measure to help students understand the principles of digital logic.It can improve the efficiency of physical experiments and decrease instrument damage caused by operating errors.CircuitVerse is an open-source and Web-based tool of circuit design and simulation for teaching purposes.And now,teachers and students in many colleges and universities use it to assist teaching and learning.Firstly,through a particular example,the features of CircuitVerse and its usage are explained.Secondly,we briefly introduce the application of CircuitVerse in our teaching as well as the following development plans.We believe that our introduction can help teachers understand the software and how to make full use of this tool.

基于相关性分离的逻辑电路敏感门定位算法

随着CMOS器件特征尺寸进入纳米量级,因高能粒子辐射等造成的电路失效问题日益严重,给电路可靠性带来严峻挑战。现阶段,准确评估集成电路可靠性,并以此为依据对电路进行容错加固,以提高电路系统可靠性变得刻不容缓。然而,由于逻辑电路中存在大量扇出重汇聚结构,由此引发的信号相关性导致可靠性评估与敏感单元定位面临困难。该文提出一种基于相关性分离的逻辑电路敏感门定位算法。先将电路划分为多个独立电路结构(ICS);以ICS为基本单元分析故障传播及信号相关性影响;再利用相关性分离后的电路模块和反向搜索算法精准定位逻辑电路敏感门单元;最后综合考虑面向输入向量空间的敏感门定位及针对性容错加固。实验结果表明,所提算法能准确、高效地定位逻辑电路敏感单元,适用于大规模及超大规模电路的可靠性评估与高效容错设计。

模拟乒乓球运动的逻辑电路设计

阐述在数字逻辑电路实验教学中引入游戏电路设计。以模拟乒乓球游戏电路的设计为例,该游戏电路综合运用计数器、移位寄存器、锁存器等逻辑器件,利用按键模拟两位选手的乒乓球拍,利用发光二极管模拟乒乓球及其运动路径,A端与B端相互击球,数码管显示选手的当前得分,游戏难度可通过改变时钟电路的频率进行调节。

基于共享总线结构的存储器内建自测试电路

随着片上系统处理的数据增多,数据存储器测试逻辑相应增加,在保证测试功能的同时减小测试电路面积是当下急需解决的问题。基于共享总线结构的存储器内建自测试(MBIST)电路,通过将多个存储器引脚信号进行复用的方式,对存储器进行层次化设计,将物理存储器拼接组成逻辑存储器模块,再整合多个逻辑存储器成为一个大的存储器集模块,MBIST控制器针对存储器集进行MBIST,从而减少测试逻辑数量以达到减小测试电路占用面积的目的。通过实验证明,该结构可以满足MBIST相关需求,相较于针对单颗存储器测试的传统MBIST电路面积减小了21.44%。该方案具有良好的实用性,可以为相关存储器测试设计提供参考。

PBL教学法在“电工电子技术”教学中的应用探究

【目的】探索符合机电专业特征的教学方法,提升机电专业学生的综合职业能力。【方法】在解读PBL教学法内涵的基础上,以“电工电子技术”课程中“组合逻辑电路的设计”这一节为例进行教学设计,包括教学目标、教学内容、教学流程、教学评价等各方面,并按照教学设计方案有序地进行了具体教学实施。【结果】1)对照班和实验班学生的理论成绩相差不大,但在基本操作、电路装配与调试以及数据处理这些方面,实验班平均成绩均高于对照班平均成绩;2)对照班和实验班学生在学习兴趣、自学能力、语言表达能力、小组协作能力、思辨能力及问题解决能力上均存在明显差异(p<0.05)。【结论】在“电工电子技术”教学中采用PBL教学法能够提升学生的学习积极性、学习成绩、操作技能以及综合实践能力,教学改革达到了预期的教学效果。

基于数字电路芯片的电子密码锁设计

产品更新迭代,现在人们使用的防盗手段,已经从传统的机械锁转变到电子密码锁。该设计提出一种基于数字电路芯片的电子密码锁设计方法,以数字芯片为核心设计逻辑电路,克服机械式密码锁密码量少、安全性差的缺点。该系统具有密码设置、按键提示音、记录输入密码错误次数、3次密码错误后触发报警和输入正确密码有指示灯等功能,具有成本低廉、功能实用的特点。

基于ICL7135的试验测试用4-1/2位数字电压表1/2位消隐功能的实现

可靠性和环境试验的性能测试中,常常需要用到以数字电压表为核心的数字化仪表。当设计一个基于ICL7135芯片的4-1/2位数字电压表电路时,需要对数字显示部分进行首位消隐的功能设计,传统的数字电压表电路中利用单片机的程序控制实现消隐,当设计电路中不采用单片机时,需考虑新的设计实现首位消隐。本文利用电压表电路中CD4511译码芯片的消隐端,结合A/D芯片的输出信号,设计一个复合逻辑门电路,实现对电路的首位正确消隐。经实验验证,复合逻辑门电路的设计思路是可行的,能保证数字电压表电路首1/2位消隐功能的实现。

列车控制电路仿真系统的开发与应用

针对轨道交通领域整列车控制电路逻辑复杂、现车调试周期长的问题,提出了具备建模高效、灵活适配、仿真测试一体化的仿真建模和测试系统,开发了列车控制电路仿真系统。该系统支持人工绘制和EB图纸导入的方式生成仿真电路图,有效解决了由于图纸数量大幅增加而带来的检查和阅读困难问题,详述了列车控制电路仿真系统的设计与实现方法,并重点阐述了开发过程中EB图纸导入自动生成电路模型、自动化测试工具和可视化仿真交互界面等方面的具体开发方案。结合实际应用案例,介绍了列车控制电路仿真系统应用于整车项目控制电路设计验证时的使用方法。目前该系统已应用于动车组、城轨等多个典型项目,仿真工程搭建效率高、系统运行顺畅,能够有效验证控制电路的正确性,应用效果良好,为后续进行整车控制功能的验证奠定了良好的基础。

DESIGN OF TERNARY ADIABATIC MULTIPLIER ON SWITCH-LEVEL

The design of ternary adiabatic multiplier adopting switch-level design techniques is proposed in this paper. First by using the theory of three essential circuit elements, the switch-level functional expressions of the carry and product circuit models, which compose one bit ternary adiabatic multiplier, are derived. Consequently, the corresponding circuit structures can be ob-tained, and the evaluation and energy recovery for ternary circuit can be realized by bootstrapped NMOS transistors and cross-memory structure. Based on the designed circuits, the four bits ter-nary adiabatic multiplier is further realized by adopting the ripple carry manner. The PSPICE simulation results indicate that the designed circuits have correct logic function and are charac-terized with distinctive low power consumption.

Logical Function Decomposition Method for Synthesis of Digital Logical System Implemented with Programmable Logic Devices (PLD)

The paper consists in the use of some logical functions decomposition algorithms with application in the implementation of classical circuits like SSI, MSI and PLD. The decomposition methods use the Boolean matrix calculation. It is calculated the implementation costs emphasizing the most economical solutions. One important aspect of serial decomposition is the task of selecting “best candidate” variables for the G function. Decomposition is essentially a process of substituting two or more input variables with a lesser number of new variables. This substitutes results in the reduction of the number of rows in the truth table. Hence, we look for variables which are most likely to reduce the number of rows in the truth table as a result of decomposition. Let us consider an input variable purposely avoiding all inter-relationships among the input variables. The only available parameter to evaluate its activity is the number of “l”s or “O”s that it has in the truth table. If the variable has only “1” s or “0” s, it is the “best candidate” for decomposition, as it is practically redundant.

Design and Implementation of an Efficient Reversible Comparator Using TR Gate

Reversible logic is a new emerging technology with many promising applications in optical information processing, low power (Complementary Metal Oxide Semiconductor) CMOS design, (De Oxy RiboNucleic Acid) DNA computing, etc. In industrial automation, comparators play an important role in segregating faulty patterns from good ones. In previous works, these comparators have been implemented with more number of reversible gates and computational complexity. All these comparators use propagation technique to compare the data. This will reduce the efficiency of the comparators. To overcome the problem, this paper proposes an efficient comparator using (Thapliyal Ranganathan) TR gate utilizing full subtraction and half subtraction algorithm which will improve the computation efficiency. The comparator design using half subtraction algorithm shows an improvement in terms of quantum cost. The comparator design using full subtraction algorithm shows effectiveness in reducing number of reversible gates required and garbage output.

“金课”建设下数字电路与逻辑设计实践教学改革

以往的数字电路与逻辑设计课程教学中注重知识的传授,实践教学多为课程配套的验证性实验。传统的基于书面考试的课程考核方式使学生的注意力集中在课程的理论知识点上,学生对数字电路与逻辑设计系统不能形成一个完整的认识。当遇到实际复杂工程问题时,既不能有效分析问题也不能解决问题,与“金课”的创新性、挑战度和高阶性的要求相差甚远。数字电路与逻辑设计实践教学改革以基于设计的工程学习为教学目标,以项目为驱动让学生学会设计构建一个完整的数字电路与逻辑设计系统。从教学内容、教学方法、教学模式、课程评价几个方面开展实质性的改革与试验,培养多维能力,激发学生兴趣,助推“金课”建设。