A novel interleaving based selected mapping （SLM） scheme to depress the relatively high peak power of transmit signals in multicarrier communications is proposed. In the scheme, a group of bit-level interleavers spa...A novel interleaving based selected mapping （SLM） scheme to depress the relatively high peak power of transmit signals in multicarrier communications is proposed. In the scheme, a group of bit-level interleavers spanning only a few bits are used to produce multiple sequences representing the same information, and one of the sequences resulting in the lowest peak-to-average power ratio （PAPR） is selected for transmission. The implementation of the scheme including the structure of the short-span interleaver is illustrated. The performance of this PAPR reduction scheme is investigated by simulations. This scheme exhibits a good PAPR reduction performance, and for signals of high level modulation, such as 16QAM and 64QAM, it approaches the best performance of all SLM schemes. Compared to the conventional interleaving SLM, this short-span interleaving SLM results in a very short time delay, requires very few register units for buffering, and can be easily implemented by hardware.展开更多
文摘A novel interleaving based selected mapping （SLM） scheme to depress the relatively high peak power of transmit signals in multicarrier communications is proposed. In the scheme, a group of bit-level interleavers spanning only a few bits are used to produce multiple sequences representing the same information, and one of the sequences resulting in the lowest peak-to-average power ratio （PAPR） is selected for transmission. The implementation of the scheme including the structure of the short-span interleaver is illustrated. The performance of this PAPR reduction scheme is investigated by simulations. This scheme exhibits a good PAPR reduction performance, and for signals of high level modulation, such as 16QAM and 64QAM, it approaches the best performance of all SLM schemes. Compared to the conventional interleaving SLM, this short-span interleaving SLM results in a very short time delay, requires very few register units for buffering, and can be easily implemented by hardware.
