Improved reduced-complexity bit and power allocation algorithms for multicarrier systems

Based on the iterative bit-filling procedure, a computationally efficient bit and power allocation algorithm is presented. The algorithm improves the conventional bit-filling algorithms by maintaining only a subset of subcarriers for computation in each iteration, which reduces the complexity without any performance degradation. Moreover, a modified algorithm with even lower complexity is developed, and equal power allocation is introduced as an initial allocation to accelerate its convergence. Simulation results show that the modified algorithm achieves a considerable complexity reduction while causing only a minor drop in performance.

Adaptive Power and Bit Allocation in Multicarrier Systems

We present two adaptive power and bit allocation algorithms for multicarrier systems in a frequency selective fading environment. One algorithm allocstes bit based on maximizing the channel capacity, another allocates bit based on minimizing the bit-error-rate （BER）. Two algorithms allocate power based on minimizing the BER. Results show that the proposed algorithms are more effective than Fischer＇s algorithm at low average signal-to-noise ration （SNR）. This indicates that our algorithms can achieve high spectral efficiency and high communication reliability during bad channel state. Results also denote the bit and power allocation of each algorithm and effects of the number of subcarriers on the BER performance.

A Novel Asymmetric Three-Phase Cascaded 21 Level Inverter Fed Induction Motor Using Multicarrier PWM with PI and Fuzzy Controller

Multilevel inverters are gaining popularity in high power applications. This paper proposes a new ladder type structure of cascaded three-phase multilevel inverter with reduced number of power semiconductor devices which is used to drive the induction motor. The ultimate aim of the paper is to produce multiple output levels with minimum number of semiconductor devices. This paper uses only 11 switches along with 3 diodes and 4 asymmetrical sources to produce an output voltage of 21 levels. The modulation technique plays a major role in commutation of the switches. Here we implement the multicarrier level shifting pulse width modulation technique to produce the commutation signals for the inverter. The proposed multilevel inverter is used to drive the three-phase induction motor. The mathematical modeling of three-phase induction motor is done using Simulink. Furthermore the PI and fuzzy logic controllers are also used to produce the reference waveform of the level shifting technique which in turn produces the commutation signals of the proposed multilevel converter. The controllers are used to control the speed of the induction motor. The effectiveness of the proposed system is proved with the help of simulation. The simulation is performed in MATLAB/Simulink. From the simulation results, it shows that the proposed multilevel inverter works properly to generate the multilevel output waveform with minimum number of semiconductor devices. The PI and fuzzy logic controller performances are evaluated using the results which indicate that with the help of controllers the harmonics has been reduced and the speed control of induction motor is achieved under different loading conditions.

A novel dynamic step size LMS optimization scheme for interference reducing in FBMC-QAM

Filter bank multicarrier quadrature amplitude modulation(FBMC-QAM)will encounter inter-ference and noise during the process of channel transmission.In order to suppress the interference in the communication system,channel equalization is carried out at the receiver.Given that the con-ventional least mean square(LMS)equilibrium algorithm usually suffer from drawbacks such as the inability to converge quickly in large step sizes and poor stability in small step sizes when searching for optimal weights,in this paper,a design scheme for adaptive equalization with dynamic step size LMS optimization is proposed,which can further improve the convergence and error stability of the algorithm by calling the Sigmoid function and introducing three new parameters to control the range of step size values,adjust the steepness of step size,and reduce steady-state errors in small step sta-ges.Theoretical analysis and simulation results demonstrate that compared with the conventional LMS algorithm and the neural network-based residual deep neural network(Res-DNN)algorithm,the adopted dynamic step size LMS optimization scheme can not only obtain faster convergence speed,but also get smaller error values in the signal recovery process,thereby achieving better bit error rate(BER)performance.

Walsh Hadamard Transform Based Transceiver Design for SC-FDMA with Discrete Wavelet Transform

This article proposes a new transceiver design for Single carrier frequency division multiple access(SCFDMA)system based on discrete wavelet transform(DWT). SCFDMA offers almost same structure as Orthogonal frequency division multiple access(OFDMA)with extra advantage of low Peak to Average Power Ratio(PAPR). Moreover,this article also suggests the application of Walsh Hadamard transform(WHT)for linear precoding(LP)to improve the PAPR performance of the system. Supremacy of the proposed transceiver over conventional Fast Fourier transform(FFT)based SCFDMA is shown through simulated results in terms of PAPR,spectral efficiency(SE)and bit error rate(BER).

A KIND OF PAPR REDUCTION METHOD BASED ON PRUNING WPM AND PTS TECHNOLOGY

Wavelet packet multicarrier system gains widespread concern because of its better resistance performance to Inter-Symbol Interference (ISI) and Inter-Carrier Interference (ICI), as well as the higher spectrum efficiency. However, multicarrier system has a high Peak to Average Power Ratio (PAPR), which will lead to many problems such as lower system performance. In order to solve the problem, a kind of PAPR reduction method based on pruning Wavelet Packet Modulation (WPM) and Partial Transmit Sequences (PTS) technology is proposed in this paper, through proper pruning of the full-tree structure of wavelet packet modulation in the PTS technology to reduce the number of nodes in the system, and finally improve the reduction effect of PAPR. Simulation results show that when Complementary Cumulative Distribution Function (CCDF) is 10 -3 , PTS based on pruning WPM compared with PTS technique and pruning technique has improved about 1 dB and 1.5 dB, which will not affect the system's Bit Error Rate (BER) performance in the wavelet packet multicarrier system.