FPGA implementation of fractal patterns classifier for multiple cardiac arrhythmias detection

This paper proposes the fractal patterns classifier for multiple cardiac arrhythmias on field-programmable gate array (FPGA) device. Fractal dimension transformation (FDT) is employed to adjoin the fractal features of QRS-complex, including the supraventricular ectopic beat, bundle branch ectopic beat, and ventricular ectopic beat. FDT with fractal dimension (FD) is addressed for constructing various symptomatic patterns, which can produce family functions and enhance features, making clear differences between normal and unhealthy subjects. The probabilistic neural network (PNN) is proposed for recognizing multiple cardiac arrhythmias. Numerical experiments verify the efficiency and higher accuracy with the software simulation in order to formulate the mathematical model logical circuits. FDT results in data self-similarity for the same arrhythmia category, the number of dataset requirement and PNN architecture can be reduced. Its simplified model can be easily embedded in the FPGA chip. The prototype classifier is tested using the MIT-BIH arrhythmia database, and the tests reveal its practicality for monitoring ECG signals.

FPGA-based acceleration for binary neural networks in edge computing

As a core component in intelligent edge computing,deep neural networks(DNNs)will increasingly play a critically important role in addressing the intelligence-related issues in the industry domain,like smart factories and autonomous driving.Due to the requirement for a large amount of storage space and computing resources,DNNs are unfavorable for resource-constrained edge computing devices,especially for mobile terminals with scarce energy supply.Binarization of DNN has become a promising technology to achieve a high performance with low resource consumption in edge computing.Field-programmable gate array(FPGA)-based acceleration can further improve the computation efficiency to several times higher compared with the central processing unit(CPU)and graphics processing unit(GPU).This paper gives a brief overview of binary neural networks(BNNs)and the corresponding hardware accelerator designs on edge computing environments,and analyzes some significant studies in detail.The performances of some methods are evaluated through the experiment results,and the latest binarization technologies and hardware acceleration methods are tracked.We first give the background of designing BNNs and present the typical types of BNNs.The FPGA implementation technologies of BNNs are then reviewed.Detailed comparison with experimental evaluation on typical BNNs and their FPGA implementation is further conducted.Finally,certain interesting directions are also illustrated as future work.

A Two-Stage Method for Routing in Field-Programmable Gate Arrays with Time-Division Multiplexing

Emerging applications widely use field-programmable gate array(FPGA)prototypes as a tool to verify modern very-large-scale integration(VLSI)circuits,imposing many problems,including routing failure caused by the limited number of connections among blocks of FPGAs therein.Such a shortage of connections can be alleviated through time-division multiplexing(TDM),by which multiple signals sharing an identical routing channel can be transmitted.In this context,the routing quality dominantly decides the performance of such systems,proposing the requirement of minimizing the signal delay between FPGA pairs.This paper proposes algorithms for the routing problem in a multi-FPGA system with TDM support,aiming to minimize the maximum TDM ratio.The algorithm consists of two major stages:(1)A method is proposed to set the weight of an edge according to how many times it is shared by the routing requirements and consequently to compute a set of approximate minimum Steiner trees.(2)A ratio assignment method based on the edge-demand framework is devised for assigning ratios to the edges respecting the TDM ratio constraints.Experiments were conducted against the public benchmarks to evaluate our proposed approach as compared with all published works,and the results manifest that our method achieves a better TDM ratio in comparison.

基于FPGA的千兆以太网协议分析技术

该文主要阐述在FPGA(Field-Programmable Gate Array)内千兆以太网协议数据流帧的生成、编码、组帧、解帧及协议帧分析,详细地阐述了BCM5421和FPGA组合的硬件设计技术、协议发生的FPGA设计技术、协议解码、过滤、性能分析的FPGA设计技术等关键技术的实现途径。

Resonance Characteristics of Piezoelectric Resonator Based on Digital Driving Circuit of Field-Programmable Gate Array

Piezoelectric resonators are widely used in frequency reference devices, mass sensors, resonant sensors(such as gyros and accelerometers), etc. Piezoelectric resonators usually work in a special resonant mode. Obtaining working resonant mode with high quality is key to improve the performance of piezoelectric resonators. In this paper, the resonance characteristics of a rectangular lead zirconium titanate(PZT) piezoelectric resonator are studied. On the basis of the field-programmable gate array(FPGA) embedded system, direct digital synthesizer(DDS) and automatic gain controller(AGC) are used to generate the driving signals with precisely adjustable frequency and amplitude. The driving signals are used to excite the piezoelectric resonator to the working vibration mode. The influence of the connection of driving electrodes and voltage amplitude on the vibration of the resonator is studied. The quality factor and vibration linearity of the resonator are studied with various driving methods mentioned in this paper. The resonator reaches resonant mode at 330 kHz by different driving methods.The relationship between resonant amplitude and driving signal amplitude is linear. The quality factor reaches over 150 by different driving methods. The results provide a theoretical reference for the efficient excitation of the piezoelectric resonator.

Searching for complete set of free resource rectangles on FPGA area based on CPTR

As a coprocessor, field-programmable gate array （FPGA） is the hardware computing processor accelerating the computing capacity of coraputers. To efficiently manage the hardware free resources for the placing of tasks on FPGA and take full advantage of the partially reconfigurable units, good utilization of chip resources is an important and necessary work. In this paper, a new method is proposed to find the complete set of maximal free resource rectangles based on the cross point of edge lines of running tasks on FPGA area, and the prove process is provided to make sure the correctness of this method.

Design and implementation of LDPC encoder based on FPGA

A low density parity check(LDPC)encoder with the codes of(8176,7154)and encoding rate of 7/8 under CCSDS standard for near space communication is designed.Based on LDPC encoding theory,the FPGA-based coding algorithm is designed.Based on the characteristics of LDPC generating matrix,the cyclic shift register is introduced as the core of the encoding circuit,and the shift-register-Adder-Accumulator(SRAA)structure is adopted to realize the fast calculation of matrix multiplication,so as to construct the encoding module with partial parallel encoding circuit as the core.In addition,the serial port input and output module,RAM storage module and control module are also designed,which together constitute the encoder system.The design scheme is implemented by FPGA hardware and verified by simulation and experiment.The results show that the test results of the designed LDPC encoder are consistent with the theoretical results.Therefore,the coding system is practical,and the design method is simple and efficient.

SIES:A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array

Neuromorphic computing is considered to be the future of machine learning,and it provides a new way of cognitive computing.Inspired by the excellent performance of spiking neural networks(SNNs)on the fields of low-power consumption and parallel computing,many groups tried to simulate the SNN with the hardware platform.However,the efficiency of training SNNs with neuromorphic algorithms is not ideal enough.Facing this,Michael et al.proposed a method which can solve the problem with the help of DNN(deep neural network).With this method,we can easily convert a well-trained DNN into an SCNN(spiking convolutional neural network).So far,there is a little of work focusing on the hardware accelerating of SCNN.The motivation of this paper is to design an SNN processor to accelerate SNN inference for SNNs obtained by this DNN-to-SNN method.We propose SIES(Spiking Neural Network Inference Engine for SCNN Accelerating).It uses a systolic array to accomplish the task of membrane potential increments computation.It integrates an optional hardware module of max-pooling to reduce additional data moving between the host and the SIES.We also design a hardware data setup mechanism for the convolutional layer on the SIES with which we can minimize the time of input spikes preparing.We implement the SIES on FPGA XCVU440.The number of neurons it supports is up to 4000 while the synapses are 256000.The SIES can run with the working frequency of 200 MHz,and its peak performance is 1.5625 TOPS.

Efficient multiuser detector based on box-constrained deregularization and its FPGA design

Multiuser detection can be described as a quadratic optimization problem with binary constraint. Many techniques are available to find approximate solution to this problem. These tech- niques can be characterized in terms of complexity and detection performance. The ＂efficient frontier＂ of known techniques include the decision-feedback, branch-and-bound and probabilistic data association detectors. The presented iterative multiuser detection technique is based on joint deregularized and box-constrained so- lution to quadratic optimization with iterations similar to that used in the nonstationary Tikhonov iterated algorithm. The deregulari- zation maximizes the energy of the solution, this is opposite to the Tikhonov regularization where the energy is minimized. However, combined with box-constraints, the deregularization forces the solution to be close to the binary set. We further exploit the box- constrained dichotomous coordinate descent （DCD） algorithm and adapt it to the nonstationary iterative Tikhonov regularization to present an efficient detector. As a result, the worst-case and aver- age complexity are reduced down to K28 and K2~ floating point operation per second, respectively. The development improves the ＂efficient frontier＂ in multiuser detection, which is illustrated by simulation results. Finally, a field programmable gate array （FPGA） design of the detector is presented. The detection performance obtained from the fixed-point FPGA implementation shows a good match to the floating-point implementation.

A real-time 5/3 lifting wavelet HD-video de-noising system based on FPGA

In accordance with the application requirements of high definition(HD) video surveillance systems,a real-time 5/3 lifting wavelet HD-video de-noising system is proposed with frame rate conversion(FRC) based on a field-programmable gate array(FPGA),which uses a 3-level pipeline paralleled 5/3 lifting wavelet transformation and reconstruction structure,as well as a fast BayesS hrink adaptive threshold filtering module.The proposed system demonstrates de-noising performance,while also balancing system resources and achieving real-time processing.The experiments show that the proposed system's maximum operating frequency(through logic synthesis and layout using Quartus 13.1 software) can reach 178 MHz,based on the Altera Company's Stratix III EP3SE80 series FPGA.The proposed system can also satisfy real-time de-noising requirements of 1920 × 1080 at60 fps HD-video sources,while also significantly improving the peak signal to noise rate of the denoising images.Compared with similar systems,the system has the advantages of high operating frequency,and the ability to support multiple source formats for real-time processing.

Implementation of motion estimator algorithm with 1/4 pixel accuracy based on FPGA

After research on the motion estimation algorithm in video coding, a motion estimator algorithm with 1/4 pixel ac- curacy is implemented based on fie/d-programmable gate array （FPGA）. The motion estimation algorithm module is made up of the 1[4 pixel interpolation module with serial input and parallel output, the three step search module and the block match- ing module, which can use relatively less Wiener filters for interpolation operation. Experiment results show that the hard- ware design has less consumption of the logical resource, higher stability and lower power consumption.

Signal processing circuit of laser gyro based on FPGA and DSP

This is a paper about laser gyro sign a l processing circuit which is designed based on field-programmable gate array(FPGA) and digital signal processor(DSP).Through a pre-amplifier circuit,FPGA and DSP,a weak current signal is converted and transferred,then sent to the computer to display the final results.Through the laser gyro performance te sting,the obtained results coincide with those of the existing methods.Thus th e d esigned circuit realizes the function of laser gyro signal processing.

主被动均衡电池管理系统设计

为了克服新能源汽车电池组在使用过程中内部单体电池充放电速率不一致问题,提出了一种基于现场可编程门阵列(field-programmable gate array,FPGA)的主被动均衡相结合的电池管理系统。该设计通过LTC6811电池采集芯片,将电压、电流、温度等数据传到FPGA进行容量估算。主控微控制单元(microcontroller unit,MCU)通过设置单体间荷电状态(state of charge,SOC)差值阈值,控制均衡电路中的回路开关的通断,使单体电池在不同容量差值时,进行不同的均衡策略。同时运用MATLAB/Simulink仿真软件搭建出核心主被动均衡电路模型,对电路的均衡方案进行仿真分析。仿真结果表明:通过采用主被动相结合的均衡策略,电池在充放电过程中均衡速度较单一均衡方式有明显的提升。可见通过主被动均衡结合的方式,能有效地提升电池均衡速度,改善电池使用效率。

BD2/GPS高精度同步时钟装置的设计与应用

针对CCD(Charge Coupled Device)相机在探测脉冲激光光斑过程中曝光时刻与脉冲激光同步的问题,提出一种利用超前预测方式同步触发CCD相机抓拍光斑图像的高精度时钟源设计方案。该装置主要采用北斗2导航系统(BD2:BeiDou2 navigation satellite system)/全球定位系统(GPS:Global Positioning System),双模接收单元提供的协调世界时(UTC:Universal Time Coordinated)时间以及高精度秒脉冲(PPS:One-Pulse Per Second)时间基准作为同步时钟装置的基准源,并结合现场可编程门阵列(FPGA:Field-Programmable Gate Array)高速时序计算与微控制单元接口技术,保证CCD相机同步抓拍时间,从而完成高精度的同步触发。实验表明,该装置可以提供微秒级时间同步精度和标准授时信息,有效地缩短了CCD相机曝光时间,得到完整清晰的高信噪比脉冲激光光斑图像。

New digital drive phase control for improving bias stability of silicon MEMS gyroscope

In order to improve the bias stability of the micro-electro mechanical system（MEMS） gyroscope and reduce the impact on the bias from environmental temperature,a digital signal processing method is described for improving the accuracy of the drive phase in the gyroscope drive mode.Through the principle of bias signal generation,it can be concluded that the deviation of the drive phase is the main factor affecting the bias stability.To fulfill the purpose of precise drive phase control,a digital signal processing circuit based on the field-programmable gate array（FPGA） with the phase-lock closed-loop control method is described and a demodulation method for phase error suppression is given.Compared with the analog circuit,the bias drift is largely reduced in the new digital circuit and the bias stability is improved from 60 to 19 °/h.The new digital control method can greatly increase the drive phase accuracy,and thus improve the bias stability.

基于机器视觉的坯布疵点实时自动检测平台

为了克服人工检测坯布疵点过程中存在的低效率、高误检率、高漏检率等问题,设计并实现了一款能兼顾实时性和准确性要求的坯布自动检测平台.该平台包括织物传动系统、光源和成像系统、图像采集与处理系统、人机交互系统4个组成部分.在详细阐述了图像采集与处理系统的设计之后,结合AR谱算法对坯布自动检测平台进行了相关调试和试验验证,结果表明该平台已实现了预期的研发要求.

便携式可在线编程雷达信号模拟器

随着雷达接收机系统的日益复杂,雷达信号模拟器日益成为现场测试中的必备工具.根据测试雷达的型号不同,或调试、测试的内容不同,对雷达信号模拟器提供的模拟信号也有着完全不同的要求.为了满足现场测试中,对具备多种信号输出能力的信号模拟器的需求,本文研究设计了一套可在线编程的便携式雷达信号模拟器.该模拟器可以按照测试需求,输出典型的杂波、目标和噪声调制信号,也可以通过universal serial bus(USB)接口与personal computer(PC)机相连,通过实时在线编程,产生测试所需的信号,提高了雷达信号模拟器的实用范围,同时也提升了雷达信号模拟器的便携性.本系统通过计算机软件系统生成雷达信号仿真数据,通过USB总线交互模块实现数据在模拟器和计算机系统之间的交互,运用field-programmable gate array(FPGA)控制模块控制数据的下载,存储和输出,利用Flash实现离电信号储存,采用四片高速RAM进行信号实时输出.本文全面阐述了雷达信号模拟系统的工作原理,介绍了该系统设计方案,着重阐述了模块间的硬件接口及控制模块.该系统体积小,便于携带,改变模拟信号类型方便,具有较好的灵活性和通用性.

New scale factor correction scheme for CORDIC algorithm

To overcome the drawbacks such as irregular circuit construction and low system throughput that exist in conventional methods, a new factor correction scheme for coordinate rotation digital computer（ CORDIC） algorithm is proposed. Based on the relationship between the iteration formulae, a new iteration formula is introduced, which leads the correction operation to be several simple shifting and adding operations. As one key part, the effects caused by rounding error are analyzed mathematically and it is concluded that the effects can be degraded by an appropriate selection of coefficients in the iteration formula. The model is then set up in Matlab and coded in Verilog HDL language. The proposed algorithm is also synthesized and verified in field-programmable gate array （FPGA）. The results show that this new scheme requires only one additional clock cycle and there is no change in the elementary iteration for the same precision compared with the conventional algorithm. In addition, the circuit realization is regular and the change in system throughput is very minimal.

Multi-channel & high-precision data acquisition devi ce for aerospace

This paper describes the detailed desi gn of data acquisition device with multi-channel and high-precision for aerosp ace.Based on detailed analysis of the advantages and disadvantages of tw o common acquisition circuits,the design factors of acquisition device focus o n accuracy,sampling rate,hardware overhead and design space.The me chanical structure of the system is divided into different card layers according to different functions and the structure has the characteristics of high reliability,conveni ence to install and scalability.To ens ure reliable operation mode,the interface uses the optocoupler isolated from th e e xternal circuit.The transmission of signal is decided by the current in the cur rent loop that consists of optocouplers between acquisition device and t est bench.In multi-channel switching circuit,by establ ishing analog multiplexer model,the selection principles of circuit modes are given.

Study on GNSS satellite signal simulator

Satellite signal simulator for global navigation satellite system(GNSS)can evaluate the accuracy of capturing,tracing and positioning of GNSS receiver.It has significant use-value in the military and civil fields.The system adopts the overall design scheme of digital signal processor(DSP)and field-programmable gate array(FPGA).It consists of four modules:industrial control computer simulation software,mid-frequency signal generator,digital-to-analog(D/A)module and radio frequency(RF)module.In this paper,we test the dynamic performance of simulator using the dynamic scenes testing method,and the signal generated by the designed simulator is primarily validated.