This paper presents an inductorless complementary-noise-canceling LNA （CNCLNA） for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The...This paper presents an inductorless complementary-noise-canceling LNA （CNCLNA） for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure. Linearity is also enhanced by employing a multiple gated transistors technique. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed CNCLNA achieves 13.5-16 dB voltage gain from 50 to 860 MHz, the noise figure is below 4.5 dB and has a minimum value of 2.9 dB, and the best PIdB is -7.5 dBm at 860 MHz. The core consumes 6 mA current with a supply voltage of 1.8 V, while the core area is only 0.2 ×0.2 mm2.展开更多
基金Project supported by the Ministry of Industry and Information Technology,China(No.2009ZX03006-009)
文摘This paper presents an inductorless complementary-noise-canceling LNA （CNCLNA） for TV tuners. The CNCLNA exploits single-to-differential topology, which consists of a common gate stage and a common source stage. The complementary topology can save power and improve the noise figure. Linearity is also enhanced by employing a multiple gated transistors technique. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed CNCLNA achieves 13.5-16 dB voltage gain from 50 to 860 MHz, the noise figure is below 4.5 dB and has a minimum value of 2.9 dB, and the best PIdB is -7.5 dBm at 860 MHz. The core consumes 6 mA current with a supply voltage of 1.8 V, while the core area is only 0.2 ×0.2 mm2.
