Unique microstructure and property of a 2024 aluminum alloy subjected to upsetting extrusion multiple processing

The microstructure and hardness of a 2024 aluminum alloy subjected tomulti-pass upsetting extrusion at ambient temperature were studied. Experimental results indicatedthat with the number of upsetting extrusion passes increasing, the grains of the alloy are graduallyrefined and the hardness increases correspondingly. After ten passes of upsetting extrusionprocessing, the grain size decreases to less than 200 nm in diameter and the sample maintains itsoriginal shape, while the hardness is double owing to equal-axial ultrafine grains and workhardening effect caused by large plastic deformation.

Multiple Node Upset in SEU Hardened Storage Cells

We study the problem of multiple node upset （MNU） using three-dimensional device simulation. The results show the transient floating node and charge lateral diffusion are the key reasons for MNU. We compare the MNU with multiple bit upset （MBU）,and find that their characteristics are different. Methods to avoid MNU are also discussed.

Angular dependence of multiple-bit upset response in static random access memories under heavy ion irradiation

Experimental evidence is presented relevant to the angular dependences of multiple-bit upset （MBU） rates and patterns in static random access memories （SRAMs） under heavy ion irradiation. The single event upset （SEU） cross sections under tilted ion strikes are overestimated by 23.9%-84.6%, compared with under normally incident ion with the equivalent linear energy transfer （LET） value of 41 MeV/（mg/cm2）, which can be partially explained by the fact that the MBU rate for tilted ions of 30° is 8.5%-9.8% higher than for normally incident ions. While at a lower LET of - 9.5 MeV/（mg/cm2）, no clear discrepancy is observed. Moreover, since the ion trajectories at normal and tilted incidences are different, the predominant double-bit upset （DBU） patterns measured are different in both conditions. Those differences depend on the LET values of heavy ions and devices under test. Thus, effective LET method should be used carefully in ground-based testing of single event effects （SEE） sensitivity, especially in MBU-sensitive devices.

Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes

This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.

Azimuthal dependence of single-event and multiple-bit upsets in SRAM devices with anisotropic layout

Experimental evidence is presented showing obvious azimuthal dependence of single event upsets(SEU) and multiple-bit upset(MBU) patterns in radiation hardened by design(RHBD) and MBU-sensitive static random access memories(SRAMs), due to the anisotropic device layouts. Depending on the test devices, a discrepancy from 24.5% to 50% in the SEU cross sections of dual interlock cell(DICE) SRAMs is shown between two perpendicular ion azimuths under the same tilt angle. Significant angular dependence of the SEU data in this kind of design is also observed, which does not fit the inverse-cosine law in the effective LET method. Ion trajectory-oriented MBU patterns are identified, which is also affected by the topological distribution of sensitive volumes. Due to that the sensitive volumes are periodically isolated by the BL/BLB contacts along the Y-axis direction, double-bit upsets along the X-axis become the predominant configuration under normal incidence.Predominant triple-bit upset and quadruple-bit upset patterns are the same under different ion azimuths(Lshaped and square-shaped configurations, respectively). Those results suggest that traditional RPP/IRPP model should be promoted to consider the azimuthal and angular dependence of single event effects in certain designs.During earth-based evaluation of SEE sensitivity, worst case beam direction, i.e., the worst case response, should be revealed to avoid underestimation of the on-orbit error rate.

Monte Carlo evaluation of spatial multiple-bit upset sensitivity to oblique incidence

We investigate the impact of heavy ion irradiation on a hypothetical static random access memory （SRAM） device. Influences of the irradiation angle, critical charge, drain-drain spacing, and dimension of device structure on the device sensitivity have been studied. These prediction and simulated results are interpreted with MUFPSA, a Monte Carlo code based on Geant4. The results show that the orientation of ion beams and device with different critical charge exert indis- pensable effects on multiple-bit upsets （MBUs）, and that with the decrease in spacing distance between adjacent cells or the dimension of the cells, the device is more susceptible to single event effect, especially to MBUs at oblique incidence.

Analysis of multiple cell upset sensitivity in bulk CMOS SRAM after neutron irradiation

In our previous studies, we have proved that neutron irradiation can decrease the single event latch-up （SEL） sensitivity of CMOS SRAM. And one of the key contributions to the multiple cell upset （MCU） is the parasitic bipolar amplification, it bring us to study the impact of neutron irradiation on the SRAM＇s MCU sensitivity. After the neutron experiment, we test the devices＇ function and electrical parameters. Then, we use the heavy ion fluence to examine the changes on the devices＇ MCU sensitivity pre- and post-neutron-irradiation. Unfortunately, neutron irradiation makes the MCU phenomenon worse. Finally, we use the electric static discharge （ESD） testing technology to deduce the experimental results and find that the changes on the WPM region take the lead rather than the changes on the parasitic bipolar amplification for the 90 nm process.

基于改进准循环码的FPGA抗辐射容错方法

针对SRAM型FPGA在辐射环境中易受高能粒子影响发生单粒子多位翻转的问题,提出一种基于改进位交织技术的(16,8)准循环码抗单粒子多位翻转容错方法。在分析FPGA的典型多位翻转错误图样的基础上,采用软容错中的错误检测与纠正思想将传统的(16,8)准循环码和改进位交织技术相结合来提高编解码的软容错能力。仿真和硬件平台试验表明,该方法可以实现对FPGA中由于单粒子效应所导致的至多五位突发错误的纠正和两位随机错误的检测,同时具有编解码不额外增加冗余位、实现简单和容错能力强的特点,为增强SRAM型FPGA在应用过程中的抗单粒子翻转能力、提高相关系统的辐照可靠性提供了可行途径。

Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

Heavy ion-induced single event upsets(SEUs)of static random access memory(SRAM), integrated with three-dimensional integrated circuit technology, are evaluated using a Monte Carlo simulation method based on the Geant4 simulation toolkit. The SEU cross sections and multiple cell upset(MCU) susceptibility of 3D SRAM are explored using different types and energies of heavy ions.In the simulations, the sensitivities of different dies of 3D SRAM show noticeable discrepancies for low linear energy transfers(LETs). The average percentage of MCUs of 3D SRAM increases from 17.2 to 32.95%, followed by the energy of ^(209)Bi decreasing from 71.77 to 38.28 MeV/u. For a specific LET, the percentage of MCUs presents a notable difference between the face-to-face and back-toface structures. In the back-to-face structure, the percentage of MCUs increases with a deeper die, compared with the face-to-face structure. The simulation method and process are verified by comparing the SEU cross sections of planar SRAM with experimental data. The upset cross sections of the planar process and 3D integrated SRAM are analyzed. The results demonstrate that the 3D SRAM sensitivity is not greater than that of the planar SRAM. The 3D process technology has the potential to be applied to the aerospace and military fields.

Heavy ion‑induced MCUs in 28nm SRAM‑based FPGAs:upset proportions,classifications,and pattern shapes

For modern scaling devices,multiple cell upsets(MCUs)have become a major threat to high-reliability field-programmable gate array(FPGA)-based systems.Thus,both performing the worst-case irradiation tests to provide the actual MCU response of devices and proposing an effective MCU distinction method are urgently needed.In this study,high-and medium-energy heavy-ion irradiations for the configuration random-access memory of 28 nm FPGAs are performed.An MCU extraction method supported by theoretical predictions is proposed to study the MCU sizes,shapes,and frequencies in detail.Based on the extraction method,the different percentages,and orientations of the large MCUs in both the azimuth and zenith directions determine the worse irradiation response of the FPGAs.The extracted largest 9-bit MCUs indicate that high-energy heavy ions can induce more severe failures than medium-energy ones.The results show that both the use of high-energy heavy ions during MCU evaluations and effective protection for the application of high-density 28 nm FPGAs in space are extremely necessary.

阱接触对28 nm SRAM单粒子多位翻转的影响

为研究纳米尺度下,特征尺寸减小和阱接触布放方式对单粒子效应电荷收集机制的影响,在北京HI-13串列加速器上开展了国产28 nm静态随机存储器(SRAM)重离子单粒子效应辐照实验研究,获得了不同线性能量转移(LET)值重离子垂直入射下的器件重离子单粒子位翻转截面、多位翻转百分比和多位翻转拓扑图形,并与65 nm SRAM实验数据进行比对,分析了28 nm SRAM重离子单粒子多位翻转物理机理.结果表明,在特征尺寸减小、工作电压降低等因素影响下,器件重离子单粒子翻转阈值减小,位翻转饱和截面明显降低,多位翻转占比增大,拓扑图形可达n行×3列,且呈现间断性的特点,结合28 nm SRAM的全局阱接触布放对电荷收集机制的影响,分析这种现象的产生源于N阱内p型金属-氧化物-半导体间电荷共享所导致的单粒子翻转再恢复.

重离子辐照引发的25 nm NAND Flash存储器数据位翻转

为研究不同注量下浮栅存储单元位翻转特点及其翻转截面变化,以及重离子入射导致的多单元翻转,以两款25 nm NAND Flash存储器为载体开展了重离子实验研究。实验结果表明,单个重离子在击中存储单元灵敏体积的情况下足以引起位翻转,位翻转比率随着注量累积基本呈线性变化。由于处于编程状态阈值电压分布低压区的存储单元倾向于在相邻或靠近的地址上集中分布,随着注量累积,这类存储单元数量迅速减少,而其他大量存储单元的翻转数增长率变化不明显,因此位翻转截面随注量累积呈下降趋势。重离子导致两款器件出现多单元翻转,多单元翻转呈现单列、双列以及列间隔等结构。利用离子电离径迹模型估算得到离子电离有效径迹半径,可以判定多单元翻转是由于一个离子的电离有效径迹覆盖了多个存储单元。

一种低功耗高可靠性辐射加固锁存器设计

为缓解因电荷共享引起的多节点翻转现象,提出了一种低功耗高可靠性的多节点翻转自恢复锁存器QNULH。QNULH锁存器包括4个反馈模块,每个模块充分利用C单元的反馈锁存数据,锁存器节点通过不同的排列组合叠加模块冗余,同时使用时钟钟控和快速通路技术,实现锁存器的低功耗高可靠性辐射加固。仿真实验结果表明,与最新的四节点翻转自恢复锁存器QNURL相比,QNULH锁存器的功耗、延迟、功耗延迟积分别降低了82.22%,1.53%,92.92%,对工艺、电源电压、温度的波动均较稳定,有较好的可靠性。

55 nm工艺静态随机存储器的软错误率预测

针对重离子诱导的55nm工艺静态随机存储器中的单粒子翻转现象,采用Geant4蒙特卡洛仿真方法对其软错误率展开研究与预测。仿真采用不同种类和能量的重离子,评估SRAM的翻转截面及多单元翻转的概率。通过分析不同能量、不同入射角度的重离子轰击所诱导的单粒子单个单元翻转与多单元翻转的比例,推导出粒子入射角度对翻转发生概率的影响规律。特别针对空间环境中的宇宙射线模型,建立一种对粒子辐射影响下的55nm工艺SRAM的软错误率的预测方法。通过与辐照试验的结果对比,证明经过校准的嵌套敏感体模型能够更准确地评估SRAM的翻转截面。

Characterization of single-event multiple cell upsets in a custom SRAM in a 65 nm triple-well CMOS technology

In this paper, the characterization of single event multiple cell upsets(MCUs) in a custom SRAM is performed in a 65 nm triple-well CMOS technology, and O(linear energy transfer(LET) = 3.1 Me V cm2/mg), Ti(LET = 22.2 Me V cm2/mg) and Ge(LET = 37.4 Me V cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100%(O), 100%(Ti) and 98.11%(Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance(ID) scheme with the error detection and correction(EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.

Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.

静态存储器同一字节多位翻转实验研究

对两种大容量静态存储器 (SRAM )HM62 812 8、HM 62 85 12进行了同一字节多位翻转 (SMU)实验研究。HI 13串列加速器提供的F、Cl及Br离子轰击样品时 ,采用网络控制的 6116 62 85 12全系列SRAM单粒子效应测试系统进行动态检测 ,得到了两种器件的单粒子翻转 (SEU )以及SMU的σ LET曲线 ,分析了LET值以及测试图形对截面的影响。

亚微米特征工艺尺寸静态随机存储器单粒子效应实验研究

利用中国原子能科学研究院重离子加速器,开展了不同特征尺寸(0.35～0.13μm)CMOS工艺、不同集成度(1M、4M、8M、16M)静态随机存储器(SRAM)单粒子翻转(SEU)和单粒子闩锁(SEL)实验研究,给出了SRAM器件的SEU、SEL截面曲线。与μm级特征尺寸的器件相比,随特征尺寸的减小,单粒子翻转更加严重。测量到了令人关注的单粒子多位翻转(MBU)效应,对翻转位数进行了统计分析。MBU对目前卫星系统采用的EDAC技术提出了挑战。

纳米DDR SRAM器件重离子单粒子效应试验研究

针对90nm和65nm DDR(双倍数率)SRAM器件,开展与纳米尺度SRAM单粒子效应相关性的试验研究。分析了特征尺寸、测试图形、离子入射角度、工作电压等不同试验条件对单粒子翻转(SEU)的影响和效应规律,并对现有试验方法的可行性进行了分析。研究表明:特征尺寸减小导致翻转截面降低,测试图形和工作电压对器件单粒子翻转截面影响不大;随着入射角度增加,多位翻转的增加导致器件SEU截面有所增大;余弦倾角的试验方法对于纳米器件的适用性与离子种类和线性能量转移(LET)值相关,具有很大的局限性。

质子核反应二次粒子引起的静态存储器单粒子翻转截面计算

研究建立了质子单粒子翻转截面计算方法。基于蒙特卡罗软件Geant4,计算分析了不同能量质子核反应产生二次粒子对有效体积带来的影响,确定了有效体积大小。计算了静态随机存取存储器的质子单粒子翻转截面和多位翻转截面。计算结果在趋势上与双参数公式所预言的相符合,并可得到很高能量质子引起的极限截面;在较低能段的数据与文献的理论和实验值相符。