Heavy ion energy influence on multiple-cell upsets in small sensitive volumes:from standard to high energies

The 28 nm process has a high cost-performance ratio and has gradually become the standard for the field of radiation-hardened devices.However,owing to the minimum physical gate length of only 35 nm,the physical area of a standard 6T SRAM unit is approximately 0.16μm^(2),resulting in a significant enhancement of multi-cell charge-sharing effects.Multiple-cell upsets(MCUs)have become the primary physical mechanism behind single-event upsets(SEUs)in advanced nanometer node devices.The range of ionization track effects increases with higher ion energies,and spacecraft in orbit primarily experience SEUs caused by high-energy ions.However,ground accelerator experiments have mainly obtained low-energy ion irradiation data.Therefore,the impact of ion energy on the SEU cross section,charge collection mechanisms,and MCU patterns and quantities in advanced nanometer devices remains unclear.In this study,based on the experimental platform of the Heavy Ion Research Facility in Lanzhou,low-and high-energy heavy-ion beams were used to study the SEUs of 28 nm SRAM devices.The influence of ion energy on the charge collection processes of small-sensitive-volume devices,MCU patterns,and upset cross sections was obtained,and the applicable range of the inverse cosine law was clarified.The findings of this study are an important guide for the accurate evaluation of SEUs in advanced nanometer devices and for the development of radiation-hardening techniques.

Influences of supply voltage on single event upsets and multiple-cell upsets in nanometer SRAM across a wide linear energy transfer range

The influences of reducing the supply voltage on single event upset(SEU) and multiple-cell upset(MCU) in two kinds of 65-nm static random access memories(SRAMs) are characterized across a wide linear energy transfer(LET) range.The results show that the influence of the voltage variation on SEU cross section clearly depends on the LET value which is above heavy ion LET threshold no matter whether the SRAM is non-hardened 6 T SRAM or radiation-hardened double dual interlocked cells(DICE) SRAM.When the LET value is lower than the LET threshold of MCU,the SEU only manifests single cell upset,the SEU cross section increases with the decrease of voltage.The lower the LET value,the higher the SEU sensitivity to the voltage variation is.Lowering the voltage has no evident influence on SEU cross section while the LET value is above the LET threshold of MCU.Moreover,the reduction of the voltage can result in a decrease in the highest-order MCU event cross section due to the decrease of charge collection efficiency of the outer sub-sensitive volume within a certain voltage range.With further scaling the feature size of devices down,it is suggested that the dependence of SEU on voltage variation should be paid special attention to for heavy ions with very low LET or the other particles with very low energy for nanometer commercial off-the-shelf(COTS) SRAM.

Impact of incident direction on neutron-induced single-bit and multiple-cell upsets in 14 nm FinFET and 65 nm planar SRAMs

Based on the BL09 terminal of China Spallation Neutron Source(CSNS),single event upset(SEU)cross sections of14 nm fin field-effect transistor(FinFET)and 65 nm quad data rate(QDR)static random-access memories(SRAMs)are obtained under different incident directions of neutrons:front,back and side.It is found that,for both technology nodes,the“worst direction”corresponds to the case that neutrons traverse package and metallization before reaching the sensitive volume.The SEU cross section under the worst direction is 1.7-4.7 times higher than those under other incident directions.While for multiple-cell upset(MCU)sensitivity,side incidence is the worst direction,with the highest MCU ratio.The largest MCU for the 14 nm FinFET SRAM involves 8 bits.Monte-Carlo simulations are further performed to reveal the characteristics of neutron induced secondary ions and understand the inner mechanisms.

Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.

Multiple bit upsets mitigation in memory by using improved hamming codes and parity codes

This paper combines improved Hamming codes and parity codes to assure the reliability of memory in presence of multiple bit upsets with low cost overhead.The redundancy bits of improved Hamming codes will be appended at the end of data bits,which eliminates the overhead of interspersing the redundancy bits at the encoder and decoder.The reliability of memory is further enhanced by the layout architecture of redundancy bits and data bits.The proposed scheme has been implemented in Verilog and synthesized using the Synopsys tools.The results reveal that the proposed method has about 19% less area penalties and 13% less power consumption comparing with the current two-dimensional error codes,and its latency of encoder and decoder is 63% less than that of Hamming codes.

Azimuthal dependence of single-event and multiple-bit upsets in SRAM devices with anisotropic layout

Experimental evidence is presented showing obvious azimuthal dependence of single event upsets(SEU) and multiple-bit upset(MBU) patterns in radiation hardened by design(RHBD) and MBU-sensitive static random access memories(SRAMs), due to the anisotropic device layouts. Depending on the test devices, a discrepancy from 24.5% to 50% in the SEU cross sections of dual interlock cell(DICE) SRAMs is shown between two perpendicular ion azimuths under the same tilt angle. Significant angular dependence of the SEU data in this kind of design is also observed, which does not fit the inverse-cosine law in the effective LET method. Ion trajectory-oriented MBU patterns are identified, which is also affected by the topological distribution of sensitive volumes. Due to that the sensitive volumes are periodically isolated by the BL/BLB contacts along the Y-axis direction, double-bit upsets along the X-axis become the predominant configuration under normal incidence.Predominant triple-bit upset and quadruple-bit upset patterns are the same under different ion azimuths(Lshaped and square-shaped configurations, respectively). Those results suggest that traditional RPP/IRPP model should be promoted to consider the azimuthal and angular dependence of single event effects in certain designs.During earth-based evaluation of SEE sensitivity, worst case beam direction, i.e., the worst case response, should be revealed to avoid underestimation of the on-orbit error rate.

Stability and performance analysis of a jump linear control system subject to digital upsets

This paper focuses on the methodology analysis for the stability and the corresponding tracking performance of a closed-loop digital jump linear control system with a stochastic switching signal. The method is applied to a flight control system. A distributed recoverable platform is implemented on the flight control system and subject to independent digital upsets. The upset processes are used to stimulate electromagnetic environments. Specifically, the paper presents the scenarios that the upset process is directly injected into the distributed flight control system, which is modeled by independent Markov upset processes and independent and identically distributed （IID） processes. A theoretical performance analysis and simulation modelling are both presented in detail for a more complete independent digital upset injection. The specific examples are proposed to verify the methodology of tracking performance analysis. The general analyses for different configurations are also proposed. Comparisons among different configurations are conducted to demonstrate the availability and the characteristics of the design.

An efficient algorithm for generating a spherical multiple-cell grid

This paper presents an efficient algorithm for generating a spherical multiple-cell(SMC)grid.The algorithm adopts a recursive loop structure and provides two refinement methods:(1)an arbitrary area refinement method and(2)a nearshore refinement method.Numerical experiments are carried out,and the results show that compared with the existing grid generation algorithm,this algorithm is more flexible and operable.

Design of Novel and Low Cost Triple-node Upset Self-recoverable Latch

With the development of semiconductor technology,the size of transistors continues to shrink.In complex radiation environments in aerospace and other fields,small-sized circuits are more prone to soft error(SE).Currently,single-node upset(SNU),double-node upset(DNU)and triple-node upset(TNU)caused by SE are relatively common.TNU’s solution is not yet fully mature.A novel and low-cost TNU self-recoverable latch(named NLCTNURL)was designed which is resistant to harsh radiation effects.When analyzing circuit resiliency,a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs.Simulation results show that the latch has full TNU self-recovery.A comparative analysis was conducted on seven latches related to TNU.Besides,a comprehensive index combining delay,power,area and self-recovery—DPAN index was proposed,and all eight types of latches from the perspectives of delay,power,area,and DPAN index were analyzed and compared.The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable,NLCTNURL is reduced by 68.23%and 57.46%respectively from the perspective of delay.From the perspective of power,NLCTNURL is reduced by 72.84%and 74.19%,respectively.From the area perspective,NLCTNURL is reduced by about 28.57%and 53.13%,respectively.From the DPAN index perspective,NLCTNURL is reduced by about 93.12%and 97.31%.The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

一种基于C单元的三节点翻转自恢复锁存器

随着集成电路中工艺尺寸的不断缩减,锁存器也越来越容易受到粒子辐射引起的三节点翻转的影响。针对该问题,基于C单元的结构,提出一种低功耗、低延时和高鲁棒性的三节点翻转并自恢复的MKEEP锁存器。通过仿真实验和PVT的波动实验表明,相对于其他拥有三节点容忍或自恢复能力的锁存器,该锁存器拥有低功耗、低延迟和更小的面积开销,且对工艺、电压和温度的敏感度较低,优势明显。

多向镦拔2219铝合金硬质相形貌观测与分析

为进一步优化2219铝合金的力学性能,采用多向镦拔工艺改善2219铝合金中硬质相形貌。随着累积变形量增加到7.9,硬质相面积占比从9.66%降低为7.37%;并且其中长径比大于3的硬质相占比由初始的83.15%降低到34.23%。基于应变梯度理论建立了长椭球硬质相的细观模型,考虑到硬质相尺度效应,当其长径比从1增加到8时,应力集中系数从3.17增大为11.67;随着变形量的增加,硬质相的尺度效应逐渐弱化。通过多向镦拔实验证明了其可以有效改善硬质相形貌;将实验结果与计算结果进行对比,证明了应变梯度理论应用于2219铝合金硬质相分析的可行性。

多楔轮毂缘多道次旋压成形工艺研究

针对传统锻后切削工艺生产多楔轮存在材料利用率低、切断齿形金属流线等问题,以某多楔轮零件为研究对象,基于旋压近净成形原理,对多楔轮毂缘制定了多道次旋压工艺方案。基于SIMUFACT软件平台建立了多道次旋压成形全流程三维有限元模型,通过数值模拟研究了各道次旋压成形过程中的毂缘区材料流动规律及增厚情况。模拟结果表明,旋压预制坯外缘在第1道次旋弯轮弧挤压作用下发生明显的弯曲和增厚,板坯整体呈“半弧形”结构,后经过第2道次旋平轮镦挤推平,板坯整体发生二次增厚并成形出满足旋齿厚度要求的毂缘筒壁;通过第3道次和第4道次旋齿工艺使毂缘筒壁金属发生转移,形成满足尺寸要求的齿形结构。根据模拟结果进行试验研究,成功试制出质量合格的多楔轮零件,验证了该成形方案的可行性。

NMOS晶体管电荷共享导致的SRAM单元单粒子翻转恢复效应研究

基于Synopsys公司的三维器件模拟软件TCAD,本文研究了NMOS晶体管电荷共享导致SRAM单元的单粒子翻转恢复(SEUR)效应。分析了NMOS晶体管电荷共享导致SEUR效应的物理机制,系统研究了NMOS晶体管偏置(如电源电压、P阱偏置电压)和工艺参数(如P+深阱掺杂浓度、P阱接触距离)对线性能量传输翻转恢复阈值(LETrec)以及单粒子翻转脉冲宽度(PWrec)的影响。研究发现:PWrec随着电源电压的增大而增大;PWrec和LETrec随着P阱偏置电压的增大而减小;LETrec随着P+深阱掺杂浓度的增大而增大;PWrec随着P阱接触与NMOS晶体管之间距离的增大而增大,而LETrec随着P阱接触与NMOS晶体管之间距离增大而减小。本文研究结论有助于优化SRAM单元抗单粒子效应设计,尤其是基于SEUR效应的SRAM单元的抗辐照加固设计提供了理论指导。

Microstructure and mechanical properties of AZ31-Mg_2Si in situ composite fabricated by repetitive upsetting

AZ31-4.6% Mg2Si （mass fraction） composite was prepared by conventional casting method. Repetitive upsetting （RU） was applied to severely deforming the as-cast composite at 400 ℃ for 1, 3, and 5 passes. Finite element analysis of the material flow indicates that deformation concentrates in the bottom region of the sample after 1 pass, and much more uniform deformation is obtained after 5 passes. During multi-pass RU process, both dendritic and Chinese script type Mg2Si phases are broken up into smaller particles owing to the shear stress forced by the matrix. With the increasing number of RU passes, finer grain size and more homogeneous distribution of Mg2Si particles are obtained along with significant enhancement in both strength and ductility. AZ31-4.6%Mg2Si composite exhibits tensile strength of 284 MPa and elongation of 9.8%after 5 RU passes at 400 ℃ compared with the initial 128 MPa and 5.4%of original AZ31-4.6%Mg2Si composite.

Multiple Node Upset in SEU Hardened Storage Cells

We study the problem of multiple node upset （MNU） using three-dimensional device simulation. The results show the transient floating node and charge lateral diffusion are the key reasons for MNU. We compare the MNU with multiple bit upset （MBU）,and find that their characteristics are different. Methods to avoid MNU are also discussed.

TC18钛合金热锻成形摩擦系数的实验研究

在TC18钛合金热锻成形过程中,摩擦系数对锻件成品率和模具服役寿命有显著影响。为了精确测定不同工艺条件下的摩擦系数,基于工艺实验结合Deform-3D有限元分析的方法,通过建立摩擦系数标定曲线,测定了TC18钛合金圆环在不同润滑条件下镦粗过程中的摩擦系数,对温度场、应变场及金属流动状态进行了分析。结果表明,在TC18钛合金热锻成形工艺过程中,干摩擦条件下的摩擦系数最大,为0.70~0.80;复合润滑布条件下的摩擦系数最小,为0.30~0.40;在保温棉+纤维布的润滑条件下,摩擦系数为0.40;保温棉润滑条件下的摩擦系数为0.60~0.70。

FinFET器件单粒子翻转物理机制研究评述

鳍式场效应晶体管(FinFET)器件由于其较高的集成度以及运算密度,已成为未来航天应用领域的重要选择。FinFET器件的辐射敏感性与其制作工艺和工作条件息息相关。为了解FinFET器件的单粒子翻转(SEU)敏感机制,文章结合国内外开展的相关研究,从SEU机理出发,分析了器件特征尺寸、电源电压和入射粒子的线性能量传输(LET)值等不同条件对器件SEU敏感性的影响,最后结合实际对FinFET器件SEU的研究发展方向进行展望。

空间混合辐射环境器件单粒子在轨错误率预估及不确定度分析方法

针对空间混合辐射对器件单粒子在轨错误率的影响,基于典型静态随机存储器利用中国原子能科学研究院HI-13串列加速器以及钴源总剂量模拟辐照试验装置开展协合效应研究,发展了一种器件在混合辐射环境下的单粒子在轨错误率计算方法。并利用该方法计算了协合效应影响下的航天器典型任务周期器件的在轨错误率,同时分析了器件在轨错误率计算中的不确定度来源并计算了在轨错误率不确定度。结果表明,对于该类型器件,空间混合辐射场导致的协合效应将降低器件单粒子在轨错误率。

130 nm 7T SOI SRAM总剂量与单粒子协和效应研究

为进一步阐明SOI器件中总剂量效应(TID)与单粒子效应(SEE)间的协和效应,本文基于SOI工艺特征尺寸为130 nm的国产7T结构SRAM进行了相关研究。通过对4组SOI SRAM开展了不同TID辐照后的SEE实验,得到器件单粒子翻转(SEU)截面随TID的变化规律。SOI SRAM的SEU截面在TID辐照后呈现明显的降低,最大在750 krad(Si)剂量辐照后下降80.5%。器件的饱和截面呈现随剂量增加而下降的趋势,最大下降19.5%,研究中未发现SEU阈值的明显变化。分析认为,延迟晶体管N5的等效关态电阻因为TID辐照而增加,该现象会造成N5的延迟作用增强,是该款器件SEU截面下降的主要原因。采用这种7T结构的SOI SRAM的抗SEE性能会随其在轨累积剂量的增加而逐渐增强,这为今后电子器件的抗辐射加固提供了启示。

两种面向宇航应用的高可靠性抗辐射加固技术静态随机存储器单元

CMOS尺寸的大幅缩小引发电路可靠性问题。该文介绍了两种高可靠的基于设计的抗辐射加固(RHBD)10T和12T抗辐射加固技术(SRAM)单元,它们可以防护单节点翻转(SNU)和双节点翻转(DNU)。10T单元主要由两个交叉耦合的输入分离反相器组成,该单元可以通过其内部节点之间的反馈机制稳定地保持存储的值。由于仅使用少量晶体管,因此其在面积和功耗方面开销也较低。基于10T单元,提出了使用4个并行存取访问管的12T单元。与10T单元相比,12T单元的读/写访问时间更短,且具有相同的容错能力。仿真结果表明,所提单元可以从任意SNU和部分DNU中恢复。此外,与先进的加固SRAM单元相比,所提RHBD 12T单元平均可以节省16.8%的写访问时间、56.4%的读访问时间和10.2%的功耗,而平均牺牲了5.32%的硅面积。