The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main ...The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.展开更多
The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communi...The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.展开更多
The performance of a single gas electron multiplier(GEM) in pure Xe at an atmospheric pressure is investigated by Particle in Cell-Monte Carlo Collision(PIC-MCC) model.The micro development processes with electrons an...The performance of a single gas electron multiplier(GEM) in pure Xe at an atmospheric pressure is investigated by Particle in Cell-Monte Carlo Collision(PIC-MCC) model.The micro development processes with electrons and ions distributions in space have been revealed.Based on the micro development processes,the macroscopic parameters such as GEM gain and the effective efficiency have also been obtained.The simulation results indicate that after tens of nanoseconds,electrons are collected by the readout electrode while the ions still exist in the gas space for several microseconds.The main signal current is formed by the electrons arriving at the readout electrode,but electrons and ions are also collected by the copper electrodes near the GEM hole and the thin Kapton film boundary.The simulated gain of GEM exponentially increases with the applied GEM voltage.With the PIC-MCC simulations,both the physical amplification and charging mechanisms in the GEM device can be well understood,which is beneficial to the device design.展开更多
A high linearity current mode multiplier/divider （CMM/D） with a wide dynamic range is presented. The proposed CMM/D is based on the voltage-current characteristic of the diode, thus wide dynamic range is achieved. I...A high linearity current mode multiplier/divider （CMM/D） with a wide dynamic range is presented. The proposed CMM/D is based on the voltage-current characteristic of the diode, thus wide dynamic range is achieved. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature and device parameters of the fabrication process. Furthermore, no extra bias current for all input signals is required and thus power saving is realized. With proper selection of establishing the input terminal, the proposed circuit can perform as a mulfifunction circuit to he operated as a multiplier/divider, without changing its topology. The proposed circuit is implemented in a 0.25μm BCD process and the chip area is 0.26 ~ 0.24 mm2. The simulation and measurement results show that the maximum static linearity error is 4-1.8% and the total harmonic distortion is 0.4% while the input current ranges from 0 to 200 μA.展开更多
A fault-tolerant circuit is required for robust quantum computing in the presence of noise.Clifford+T circuits are widely used in fault-tolerant implementations.As a result,reducing T-depth,T-count,and circuit width h...A fault-tolerant circuit is required for robust quantum computing in the presence of noise.Clifford+T circuits are widely used in fault-tolerant implementations.As a result,reducing T-depth,T-count,and circuit width has emerged as important optimization goals.A measure-and-fixup approach yields the best T-count for arithmetic operations,but it requires quantum measurements.This paper proposes approximate Toffoli,TR,Peres,and Fredkin gates with optimized T-depth and T-count.Following that,we implement basic arithmetic operations such as quantum modular adder and subtractor using approximate gates that do not require quantum measurements.Then,taking into account the circuit width,T-depth,and T-count,we design and optimize the circuits of two multipliers and a divider.According to the comparative analysis,the proposed multiplier and divider circuits have lower circuit width,T-depth,and T-count than the current works that do not use the measure-and-fixup approach.Significantly,the proposed second multiplier produces approximately 77%T-depth,60%T-count,and 25%width reductions when compared to the existing multipliers without quantum measurements.展开更多
目的 探讨rSIG/A(reverse shock index multiplied by Glasgow coma score divided by age)在急诊创伤患者中对预后的评估价值。方法 收集2012年1月至2014年3月浙江大学医学院附属第一医院急诊收治的1060例创伤患者的临床资料,以28d预...目的 探讨rSIG/A(reverse shock index multiplied by Glasgow coma score divided by age)在急诊创伤患者中对预后的评估价值。方法 收集2012年1月至2014年3月浙江大学医学院附属第一医院急诊收治的1060例创伤患者的临床资料,以28d预后为结局,将患者分为存活组和死亡组;根据rSIG/A最佳截断值,将患者分为rSIG/A≤0.34组和rSIG/A>0.34组;根据急性生理学和慢性健康状况评价Ⅱ(acute physiology and chronic health evaluation Ⅱ,APACHE Ⅱ)评分最佳截断值,将患者分为APACHE Ⅱ评分≤12分组、APACHE Ⅱ评分>12分组。回顾性分析其生命体征、格拉斯哥昏迷评分(Glasgow coma score,GCS)、APACHE Ⅱ评分、rSIG/A、病死率等指标,并比较rSIG/A与APACHE Ⅱ评分间的关系,分析其与预后的关系。结果 存活组患者的rSIG/A、GCS评分均高于死亡组,APACHE Ⅱ评分低于死亡组(P<0.01)。rSIG/A与APACHE Ⅱ评分对创伤患者病死率均有一定的预测价值(曲线下面积分别为0.866、0.856),但两者间差异无统计学意义。rSIG/A≤0.34组患者的APACHE Ⅱ评分、病死率均大于rSIG/A>0.34组(P<0.01),APACHE Ⅱ评分≤12分组患者的rSIG/A值大于APACHE Ⅱ评分>12分组,病死率小于APACHE Ⅱ评分>12分组(P<0.01)。创伤患者rSIG/A值与APACHE Ⅱ评分呈负相关(r=–0.574,P<0.01)。rSIG/A值(OR=0.008,95%CI:0~0.620,P=0.030)与死亡呈负相关;APACHE Ⅱ评分(OR=1.106,95%CI:1.009~1.213,P=0.031)与死亡呈正相关(P<0.05)。结论 rSIG/A、APACHE Ⅱ评分在创伤患者伤情严重程度及预后评估方面有一定的价值,但由于rSIG/A具有无创、简便、快速及持续评估的优势,因此,更加值得在急诊推广。展开更多
基金The National Natural Science Foundation of China(No60472057)
文摘The design of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for transmitter and receiver in IEEE 802. 11 a standard, is investigated. The main steps in very large-scale integration （VLSI） design flow such as logic synthesis, floorplan and placement ＆ routing （P ＆ R） are introduced. By back-annotating the back-end information to the front-end design, the custom wire-load model is created and used for optimizing the design flow under deep submicron technology. The programmable frequency divider is implemented based on Artisan TSMC （Taiwan Semicoductor Manufacturing Co. Ltd. ）0. 18μm CMOS （complementary metal-oxide-semiconductor） standard cells and fabricated. The Chip area is 1 360. 5μm^2 and can work in the range of 100 to 200 MHz. The measurement results indicate that the design conforms to the frequency division precision.
基金The National Natural Science Foundation of China(No.60472057)
文摘The implementation of a programmable frequency divider, which is one of the components of the phase-locked loop （PLL） frequency synthesizer for digital video broadcastingterrestrial （DVB-T） and other modem communication systems, is presented. By cooperating with a dual-modulus prescaler, this divider can realize an integer frequency division from 926 to 1 387. Besides the traditional standard cell design flow, such as logic synthesis, placement and routing, the interactions between front-end and back-end are also considered to optimize the design flow under deep submicron technology. By back-annotating the back-end information to front-end design, a custom wire-load model is created which is more practical compared with the default model. This divider has been fabricated in TSMC 0. 18μm CMOS technology using Artisan standard cell library. The chip area is 675 μm × 475 μm and the power consumption is about 2 mW under a 1.8 V power supply. Measurement results show that it works correctly and can realize a frequency division with high precision.
基金Supported by the National Natural Science Foundation of China under Contract No.50907009 and 60871015the Foundation for Excellent Youth Scholars of Southeast University
文摘The performance of a single gas electron multiplier(GEM) in pure Xe at an atmospheric pressure is investigated by Particle in Cell-Monte Carlo Collision(PIC-MCC) model.The micro development processes with electrons and ions distributions in space have been revealed.Based on the micro development processes,the macroscopic parameters such as GEM gain and the effective efficiency have also been obtained.The simulation results indicate that after tens of nanoseconds,electrons are collected by the readout electrode while the ions still exist in the gas space for several microseconds.The main signal current is formed by the electrons arriving at the readout electrode,but electrons and ions are also collected by the copper electrodes near the GEM hole and the thin Kapton film boundary.The simulated gain of GEM exponentially increases with the applied GEM voltage.With the PIC-MCC simulations,both the physical amplification and charging mechanisms in the GEM device can be well understood,which is beneficial to the device design.
基金Project supported by the Important National S&T Special Project of China(Nos.2009ZX01031-003-003,51308020305)
文摘A high linearity current mode multiplier/divider （CMM/D） with a wide dynamic range is presented. The proposed CMM/D is based on the voltage-current characteristic of the diode, thus wide dynamic range is achieved. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature and device parameters of the fabrication process. Furthermore, no extra bias current for all input signals is required and thus power saving is realized. With proper selection of establishing the input terminal, the proposed circuit can perform as a mulfifunction circuit to he operated as a multiplier/divider, without changing its topology. The proposed circuit is implemented in a 0.25μm BCD process and the chip area is 0.26 ~ 0.24 mm2. The simulation and measurement results show that the maximum static linearity error is 4-1.8% and the total harmonic distortion is 0.4% while the input current ranges from 0 to 200 μA.
基金This work was supported by the National Natural Science Foundation of China(Grant Nos.61762012,61763014,and 62062035)the Science and Technology Project of Guangxi(Grant No.2020GXNSFDA238023).
文摘A fault-tolerant circuit is required for robust quantum computing in the presence of noise.Clifford+T circuits are widely used in fault-tolerant implementations.As a result,reducing T-depth,T-count,and circuit width has emerged as important optimization goals.A measure-and-fixup approach yields the best T-count for arithmetic operations,but it requires quantum measurements.This paper proposes approximate Toffoli,TR,Peres,and Fredkin gates with optimized T-depth and T-count.Following that,we implement basic arithmetic operations such as quantum modular adder and subtractor using approximate gates that do not require quantum measurements.Then,taking into account the circuit width,T-depth,and T-count,we design and optimize the circuits of two multipliers and a divider.According to the comparative analysis,the proposed multiplier and divider circuits have lower circuit width,T-depth,and T-count than the current works that do not use the measure-and-fixup approach.Significantly,the proposed second multiplier produces approximately 77%T-depth,60%T-count,and 25%width reductions when compared to the existing multipliers without quantum measurements.
