DSP operation in a Biomedical related therapeutic hardware need to beperformed with high accuracy and with high speed. Portable DSP hardware’s likepulse/heart beat detectors must perform with reduced operational powe...DSP operation in a Biomedical related therapeutic hardware need to beperformed with high accuracy and with high speed. Portable DSP hardware’s likepulse/heart beat detectors must perform with reduced operational power due to lack ofconventional power sources. This work proposes a hybrid biomedical hardware chip inwhich the speed and power utilization factors are greatly improved. Multipliers are thecore operational unit of any DSP SoC. This work proposes a LUT based unsignedmultiplication which is proven to be efficient in terms of high operating speed. For n bitinput multiplication n*n memory array of 2 n bit size is required to memorize all thepossible input and output combination. Various literature works claims to be achieve highspeed multiplication with reduced LUT size by integrating a barrel shifter mechanism.This paper work address this problem, by reworking the multiplier architecture with aparallel operating pre-processing unit which used to change the multiplier and multiplicandorder with respect to the number of computational addition and subtraction stages required.Along with LUT multiplier a low power bus encoding scheme is integrated to limit the powerconstraint of the on chip DSP unit. This paper address both the speed and power optimizationtechniques and tested with various FPGA device families.展开更多
文摘DSP operation in a Biomedical related therapeutic hardware need to beperformed with high accuracy and with high speed. Portable DSP hardware’s likepulse/heart beat detectors must perform with reduced operational power due to lack ofconventional power sources. This work proposes a hybrid biomedical hardware chip inwhich the speed and power utilization factors are greatly improved. Multipliers are thecore operational unit of any DSP SoC. This work proposes a LUT based unsignedmultiplication which is proven to be efficient in terms of high operating speed. For n bitinput multiplication n*n memory array of 2 n bit size is required to memorize all thepossible input and output combination. Various literature works claims to be achieve highspeed multiplication with reduced LUT size by integrating a barrel shifter mechanism.This paper work address this problem, by reworking the multiplier architecture with aparallel operating pre-processing unit which used to change the multiplier and multiplicandorder with respect to the number of computational addition and subtraction stages required.Along with LUT multiplier a low power bus encoding scheme is integrated to limit the powerconstraint of the on chip DSP unit. This paper address both the speed and power optimizationtechniques and tested with various FPGA device families.
