Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU...Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.展开更多
More than 10,000 carbon nanotube field-effect transistors(CNTFETs)have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes.These tran...More than 10,000 carbon nanotube field-effect transistors(CNTFETs)have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes.These transistors offer advantages such as high carrier mobility,large saturation velocity,low intrinsic capacitance,flexibility,and transparency.The three-dimensional multilayer structure of the CNTFET semiconductor chip,along with ongoing research in CNTFET manufacturing processes,increases the potential for creating a hybrid MOSFET-CNTFET semiconductor chip.This chip combines conventional metal-oxide-semiconductor field-effect transistors(MOSFETs)and CNTFETs in one integrated system.This paper discusses a methodology to design 6T binary static random-access memory(SRAM)using a hybrid MOSFET-CNTFET.This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAM by leveraging existing MOSFET SRAM or CNTFET SRAM design approaches.Additionally,this paper compares its performance with conventional MOSFET SRAM and CNTFET SRAM designs.展开更多
文摘Single event multiple-cell upsets（MCU） increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.
基金supported by Seokyeong University in 2022.The EDA tool was supported by the IC Design Education Center(IDEC),Korea.
文摘More than 10,000 carbon nanotube field-effect transistors(CNTFETs)have been successfully integrated into one semiconductor chip using conventional semiconductor design procedures and manufacturing processes.These transistors offer advantages such as high carrier mobility,large saturation velocity,low intrinsic capacitance,flexibility,and transparency.The three-dimensional multilayer structure of the CNTFET semiconductor chip,along with ongoing research in CNTFET manufacturing processes,increases the potential for creating a hybrid MOSFET-CNTFET semiconductor chip.This chip combines conventional metal-oxide-semiconductor field-effect transistors(MOSFETs)and CNTFETs in one integrated system.This paper discusses a methodology to design 6T binary static random-access memory(SRAM)using a hybrid MOSFET-CNTFET.This paper introduces a method for designing a hybrid MOSFET-CNTFET SRAM by leveraging existing MOSFET SRAM or CNTFET SRAM design approaches.Additionally,this paper compares its performance with conventional MOSFET SRAM and CNTFET SRAM designs.
