Three-Dimensional Cooperative Localization via Space-Air-Ground Integrated Networks

The space-air-ground integrated network(SAGIN)combines the superiority of the satellite,aerial,and ground communications,which is envisioned to provide high-precision positioning ability as well as seamless connectivity in the 5G and Beyond 5G(B5G)systems.In this paper,we propose a three-dimensional SAGIN localization scheme for ground agents utilizing multi-source information from satellites,base stations and unmanned aerial vehicles(UAVs).Based on the designed scheme,we derive the positioning performance bound and establish a distributed maximum likelihood algorithm to jointly estimate the positions and clock offsets of ground agents.Simulation results demonstrate the validity of the SAGIN localization scheme and reveal the effects of the number of satellites,the number of base stations,the number of UAVs and clock noise on positioning performance.

Design and implementation of GM- APD array readout circuit for infrared imaging

Based on an avalanche photodiode（ APD） detecting array working in Geiger mode（ GM-APD）, a high-performance infrared sensor readout integrated circuit（ ROIC） used for infrared 3D（ three-dimensional） imaging is proposed. The system mainly consists of three functional modules, including active quenching circuit（ AQC）, time-to-digital converter（ TDC） circuit and other timing controller circuit. Each AQC and TDC circuit together constitutes the pixel circuit. Under the cooperation with other modules, the current signal generated by the GM-APD sensor is detected by the AQC, and the photon time-of-flight（ TOF） is measured and converted to a digital signal output to achieve a better noise suppression and a higher detection sensitivity by the TDC. The ROIC circuit is fabricated by the CSMC 0. 5 μm standard CMOS technology. The array size is 8 × 8, and the center distance of two adjacent cells is 100μm. The measurement results of the chip showthat the performance of the circuit is good, and the chip can achieve 1 ns time resolution with a 250 MHz reference clock, and the circuit can be used in the array structure of the infrared detection system or focal plane array（ FPA）.

An optimal stacking order for mid-bond testing cost reduction of 3D IC

In order to solve the problem that the testing cost of the three-dimensional integrated circuit(3D IC)is too high,an optimal stacking order scheme is proposed to reduce the mid-bond test cost.A new testing model is built with the general consideration of both the test time for automatic test equipment(ATE)and manufacturing failure factors.An algorithm for testing cost and testing order optimization is proposed,and the minimum testing cost and optimized stacking order can be carried out by taking testing bandwidth and testing power as constraints.To prove the influence of the optimal stacking order on testing costs,two baselines stacked in sequential either in pyramid type or in inverted pyramid type are compared.Based on the benchmarks from ITC 02,experimental results show that for a 5-layer 3D IC,under different constraints,the optimal stacking order can reduce the test costs on average by 13%and 62%,respectively,compared to the pyramid type and inverted pyramid type.Furthermore,with the increase of the stack size,the test costs of the optimized stack order can be decreased.

RF-TSV DESIGN, MODELING AND APPLICATION FOR 3D MULTI-CORE COMPUTER SYSTEMS

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.

Some Tools to Model Ground or Supply Bounces Induced in and out of Heterogeneous Integrated Circuits

Electrical ground looks simple on a schematic; unfortunately, the actual performance of a circuit is dictated by its layout （and by its printed-circuit-board）. When the ground node moves, system performance suffers and the system radiates electromagnetic interferences. But the understanding of the physics of ground noise can provide an intuitive sense for reducing the problem. Ground bounce can produce transients with amplitudes of volts; most often changing magnetic flux is the cause; in this work, the authors use a Finite-Difference Time-Domain to begin to understand such phenomena. Additionally, predicting substrate cross-talks in mixed-signal circuits has become a critical issue to preserve signal integrity in future integrated systems. Phenomena that involve parasitic signal propagation into the substrate are discussed. A simple methodology to predict the substrate cross-talk and some associated tools are presented. Finally, the authors indicate a stochastic method which could grasp both outer or inner RF （Radio-Frequency） radiations and substrate parasites.

一种面向通信特征的3D NoC体系结构设计

三维集成电路(three dimensional integrated circuit,3DIC)和片上网络(network on chip,NoC)是集成电路设计发展的两个趋势.将两者结合的三维片上网络(three dimensional networks on chip,3DNoC)是当前研究的热点之一.针对现有3DNoC的研究没有充分关注硅片内与硅片间的异构通信特征.提出了面向通信特征的硅片间单跳步(single hop inter dies,SHID)体系结构,该结构采用异构拓扑结构和硅片间扩展路由器(express inter dies router,EIDR).通过实验数据的分析表明,与3DMesh和NoC-Bus这两种已有的3DNoC结构相比,SHID结构有以下特点:1)延迟较低,4层堆叠时比3D-Mesh低15.1%,比NoC-Bus低11.5%;2)功耗与NoC-Bus相当,比3D-Mesh低10%左右;3)吞吐率随堆叠层数增加下降缓慢,16层堆叠时吞吐率比3D-Mesh高66.98%,比NoC-Bus高314.49%.SHID体系结构同时具备性能和可扩展性的优势,是未来3DNoC体系结构良好设计选择.

Efficient Hierarchical Algorithm for Mixed Mode Placement in Three Dimensional Integrated Circuit Chip Designs

Hierarchical art was used to solve the mixed mode placement for three dimensional （3-D） integrated circuit design. The 3-D placement flow stream includes hierarchical clustering, hierarchical 3-D floorplanning, vertical via mapping, and recursive two dimensional （2-D） global/detailed placement phases. With state-of-the-art clustering and de-clustering phases, the design complexity was reduced to enhance the placement algorithm efficiency and capacity. The 3-D floorplanning phase solved the layer assignment problem and controlled the number of vertical vias. The vertical via mapping transformed the 3-D placement problem to a set of 2-D placement sub-problems, which not only simplifies the original 3-D placement problem, but also generates the vertical via assignment solution for the routing phase. The design optimizes both the wire length and the thermal load in the floorplan and placement phases to improve the performance and reliability of 3-D integrate circuits. Experiments on IBM benchmarks show that the total wire length is reduced from 15% to 35% relative to 2-D placement with two to four stacked layers, with the number of vertical vias minimized to satisfy a pre-defined upper bound constraint. The maximum temperature is reduced by 16% with two-stage optimization on four stacked layers.

Speeding up carbon nanotube integrated circuits through three-dimensional architecture

Semiconducting carbon nanotube (CNT) field effect transistor (FET) is attractive for constructing three-dimensional (3D) integrated circuits (ICs) because of its low-temperature processes and low power dissipation. However, CNT based 3D ICs reported usually suffered from lower performance than that of monolayer CNT ICs. In this work, we develop a 3D IC technology through integrating multi-layer high performance CNT film FETs into one chip, and show that it promotes the operation speed of CNT based 3D ICs considerably. We also explore the advantage on ICs of 3D architecture, which brings 38% improvement on speed over two-dimensional (2D) one. Specially, we demonstrate the fabrication of 3D five-stage ring-oscillator circuits with an oscillation frequency of up to 680 MHz and stage delay of 0.15 ns, which represents the highest speed of 3D CNT-based ICs.

Analysis and optimization of TSV–TSV coupling in three-dimensional integrated circuits

Through silicon via （TSV）-TSV coupling is detrimental to the performance of three-dimensional （3D） integrated circuits （ICs） with the major negative effect of introducing coupling noise. In order to obtain an accurate estimation of the coupling level from TSV-TSV in the early design stage, this paper first proposes an impedance- level model of the coupling channel between TSVs based on a two-port network, and then derives the formula of the coupling coefficient to describe the TSV-TSV coupling effect. The accuracy of the formula is validated by comparing the results with 3D full-wave simulations. Furthermore, a design technique for optimizing the coupling between adjacent coupled signal TSVs is proposed. Through SPICE simulations, the proposed technique shows its feasibility to reduce the coupling noise for both a simple TSV-TSV circuit and a complicated circuit with more TSVs, and demonstrates its potential for designers in achieving the goal of improving the electrical pertbrmance of3D ICs.

电磁脉冲攻击下片上配电网络IR Drop分析方法

电磁脉冲攻击对集成电路的安全具有很强的威胁性.为了有效地抵御电磁脉冲攻击,针对片上配电网络易受电磁脉冲影响的问题,提出了一种电磁脉冲攻击下片上配电网络IRdrop分布的分析方法.首先,在集成电路布局规划阶段,基于有限元仿真构建片上配电网络模型和电磁脉冲攻击模型,仿真获得电磁脉冲下配电网络上感应电流密度的分布并计算感应电流,然后将感应电流加载到配电网络模型上,使用IR分析工具分析IRdrop分布.基于TSMC180 nm工艺版图的IR drop分析结果显示,电磁脉冲攻击能够在电源和地网络中引入2.3 V以上的IR drop.与现有基于电流分布理论值的分析方法相比,该分析方法能够更准确地获取电磁脉冲下配电网络中的IR drop分布.该分析方法可用于指导改进配电网络的设计,提升抗电磁脉冲攻击能力.实验结果显示,增加一组供电端口后,电源和地网络中的最大IR drop分别降低了28%和24%.

Circuit modeling and performance analysis of SWCNT bundle 3D interconnects

Metallic carbon nanotubes （CNTs） have been proposed as a promising alternative to Cu interconnects in future integrated circuits （ICs） for their remarkable conductive, mechanical and thermal properties. Compact equiv alent circuit models for single-walled carbon nanotube （SWCNT） bundles are described, and the performance of SWCNT bundle interconnects is evaluated and compared with traditional Cu interconnects at different interconnect levels for through-silicon-via-based three dimensional （3D） ICs. It is shown that at a local level, CNT interconnects exhibit lower signal delay and smaller optimal wire size. At intermediate and global levels, the delay improvement becomes more significant with technology scaling and increasing wire lengths. For 1 mm intermediate and 10 mm global level interconnects, the delay of SWCNT bundles is only 49.49% and 52.82% that of the Cu wires, respec tively.

Development of a viable 3D integrated circuit technology

Three-dimensional integrated circuit technology with transistors stacked on top of one an-other in multi-layer silicon film has always been a vision in the future technology direction. While the idea is simple, the technique to obtain high performance multi-layer transistors is extraordinarily diffi-cult. Not until recently does such technology become feasible. In this paper, the background and vari-ous techniques to form three-dimensional circuits will be reviewed. Recent development of a simple and promising technology to achieve three-dimensional integration using Metal-Induced-Lateral-Crystalliza-tion will be described. Preliminary results of 3D inverters will also be provided to demonstrate the viabil-ity for 3D integration.

三维微电子学综述

三维微电子学主要研究三维集成电路的设计与制造。文章讨论了三维集成电路的概念、发明思想、结构、优点、制造及其挑战和应用等。三维微电子技术必将成为未来发展的新兴技术。

集成电路产业研发合作网络特征分析——基于产业链视角

在产业链高端获得高附加值是摆脱“低端锁定”的必经途径。集成电路产业链不同环节具有不同的技术要求和研发需求,目前有关嵌入产业链后研发合作情况的研究不足。从产业链视角建立集成电路产业研发合作网络,采用复杂网络理论及分析方法,对嵌入产业链前后的网络规模、小世界性、无标度特征及节点影响力范围和主体特征进行分析,结果发现:集成电路产业发展具有明显的价值链研发合作特征,且围绕固定核心企业的合作网络展开,网络中的核心节点对产业进化具有重大影响,但我国在集成电路产业链研发合作网络中尚未形成影响。最后,提出增强我国集成电路产业竞争力的对策建议。

三维结构可重构阵列在线自诊断与容错方法

目前传统的可重构阵列容错方法一般需要控制器来完成重构控制,容错重构控制算法复杂,资源利用率不高,因此提出一种面向三维结构的可重构阵列分布式自主容错方法。系统由相同的电子细胞以三维结构组成,每个细胞能进行故障定位且实现故障自修复;采用基于广度优先布线算法的重布线机制在三维细胞阵列中寻找最近冗余细胞;冗余细胞按比例均匀分布在三维阵列中,可增加容错重构控制过程的灵活性,缩短重构时间。以4位并行乘法器电路为例,对可重构阵列的功能和容错能力进行验证,实验结果表明该方法能够实现三维可重构阵列分布式自主故障诊断与修复,可容错多次故障且容错重构时间短,冗余资源利用率高。

芯片级集成微系统发展现状研究

概要介绍了芯片级集成微系统的内涵和近期发展态势,分析了它的技术特点,对相关的新技术、新结构和新器件的技术问题作了初步的分析与探讨,为发展新一代微小型电子武器系统提供一部分技术信息。

一种超小型7～8.5 GHz GaAs多功能芯片

随着微波T/R组件小型化需求的增加,微波单片集成电路（MMIC）向小型化和多功能发展。基于GaAs E/D PHEMT工艺成功研制了一款超小型7~8.5 GHz幅相控制多功能芯片。片上集成了T/R开关、6 bit数字移相器、6 bit数字衰减器、增益放大器和并行驱动器。通过在开关和放大器的匹配电路中较多地使用集总元件以及通过电磁场验证优化版图布局,实现了芯片的小型化。测试结果表明,多功能芯片的接收状态增益大于0dB,1 dB压缩输出功率（P-1）大于12 dBm;发射状态增益大于1 dB,1 dB压缩输出功率大于13 dBm。在接收和发射状态下,移相64态均方根（RMS）误差小于1.5°,衰减64态RMS误差小于0.4 dB,输入输出回波损耗小于-14 dB。裸片尺寸为3.50 mm×2.55 mm×0.07 mm。

建立在De Bruijn图架构上的三维片上网络设计

提出一种基于De Bruijn图的新型三维片上网络架构方式,利用De Bruijn图直径短、路由简单及容错等特性,实现三维片上网络水平面网络和虚平面网络相结合的分层架构与容错路由算法。利用仿真,在均匀流量和热点流量模型下将该架构与传统架构进行仿真与性能比较,结果表明,与传统的3D_Mesh、XNoTs等架构相比,基于De Bruijn图的三维片上网络架构方式具有较小的网络平均延时与良好的可扩展性。

三维任意裂隙网络渗流模型及其解法

首先,分析三维裂隙网络渗流分析模型需解决的2个关键问题,即如何获得结构面网络相交形成的裂隙渗流通道、如何计算二维任意形态区域的渗流问题。采用全空间块体搜索(三维块体切割)技术,得到封闭块体的边界就是渗流通道,块体边界的连接关系就是渗流有限元计算节点的连接关系;块体边界的裂隙面(或临空面)由不同形态、不同数量的回路构成,将每个回路上的渗流考虑为二维连续介质渗流,在面的局部坐标系下,通过单纯形积分解决任意形态回路上的渗流问题。然后,根据计算节点连接关系,形成总体渗流矩阵和渗流控制方程后就可实现三维任意结构面网络渗流计算。最后,采用算例对理论分析过程和计算程序进行检验,并将三维结构面网络渗流分析结果应用到块体系统渐进失稳分析中。