Speeding up the MATLAB complex networks package using graphic processors

The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units （GPU）. This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3x. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research.

SDN-Based Switch Implementation on Network Processors

Virtualization is the key technology of cloud computing. Network virtualization plays an important role in this field. Its performance is very relevant to network virtualizing. Nowadays its implementations are mainly based on the idea of Software Define Network (SDN). Open vSwitch is a sort of software virtual switch, which conforms to the OpenFlow protocol standard. It is basically deployed in the Linux kernel hypervisor. This leads to its performance relatively poor because of the limited system resource. In turn, the packet process throughput is very low.In this paper, we present a Cavium-based Open vSwitch implementation. The Cavium platform features with multi cores and couples of hard ac-celerators. It supports zero-copy of packets and handles packet more quickly. We also carry some experiments on the platform. It indicates that we can use it in the enterprise network or campus network as convergence layer and core layer device.

SimNP: A Flexible Platform for the Simulation of Network Processing Systems

Network processing plays an important role in the development of Internet as more and more complicated applications are deployed throughout the network. With the advent of new platforms such as network processors (NPs) that incorporate novel architectures to speedup packet processing, there is an increasing need for an efficient method to facilitate the study of their performance. In this paper, we present a tool called SimNP, which provides a flexible platform for the simulation of a network processing system in order to provide information for workload characterization, architecture development, and application implementation. The simulator models several architectural features that are commonly employed by NPs, including multiple processing engines (PEs), integrated network interface and memory controller, and hardware accelerators. ARM instruction set is emulated and a simple memory model is provided so that applications implemented in high level programming language such as C can be easily compiled into an executable binary using a common compiler like gcc. Moreover, new features or new modules can also be easily added into this simulator. Experiments have shown that our simulator provides abundant information for the study of network processing systems.

High-Level Portable Programming Language for Optimized Memory Use of Network Processors

Network processors (NPs) are widely used for programmable and high-performance networks;however, the programs for NPs are less portable, the number of NP program developers is small, and the development cost is high. To solve these problems, this paper proposes an open, high-level, and portable programming language called “Phonepl”, which is independent from vendor-specific proprietary hardware and software but can be translated into an NP program with high performance especially in the memory use. A common NP hardware feature is that a whole packet is stored in DRAM, but the header is cached in SRAM. Phonepl has a hardware-independent abstraction of this feature so that it allows programmers mostly unconscious of this hardware feature. To implement the abstraction, four representations of packet data type that cover all the packet operations (including substring, concatenation, input, and output) are introduced. Phonepl have been implemented on Octeon NPs used in plug-ins for a network-virtualization environment called the VNode Infrastructure, and several packet-handling programs were evaluated. As for the evaluation result, the conversion throughput is close to the wire rate, i.e., 10 Gbps, and no packet loss (by cache miss) occurs when the packet size is 256 bytes or larger.

Architecture-level performance/power tradeoff in network processor design

Network processors are used in the core node of network to flexibly process packet streams. With the increase of performance, the power of network processor increases fast, and power and cooling become a bottleneck. Architecture-level power conscious design must go beyond low-level circuit design. Architectural power and performance tradeoff should be considered at the same time. Simulation is an efficient method to design modern network processor before making chip. In order to achieve the tradeoff between performance and power, the processor simulator is used to design the architecture of network processor. Using Netbench,Commubench benchmark and processor simulator—SimpleScalar, the performance and power of network processor are quantitatively evaluated. New performance tradeoff evaluation metric is proposed to analyze the architecture of network processor. Based on the high performance Intel IXP 2800 Network processor configuration, optimized instruction fetch width and speed、instruction issue width, instruction window size are analyzed and selected. Simulation results show that the tradeoff design method makes the usage of network processor more effectively. The optimal key parameters of network processor are important in architecture-level design. It is meaningful for the next generation network processor design.

Reconfigurable Communication Processor: A New Approach for Network Processor

As the traditional RISC+ASIC/ASSP approach for network processor design can not meet the today’s requirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost the performance to ASIC level while reserve the programmability of the traditional RISC based system. This paper covers both the hardware architecture and the software development environment architecture.

基于NP芯片的SRv6网络切片设计与实现

随着云和互联网的快速发展,用户对网络业务的需求也呈现出多样化的趋势,为实现不同业务的多样化需求,SRv6网络切片应运而生。基于网络处理器的SRv6网络切片功能在转发过程中引入全局切片标识,并将其封装于IPv6的逐跳扩展头中。通过切片标识与VLAN子接口的绑定关系来区分不同的转发资源,并与子接口限速相结合实现对不同业务流量的差异化控制,达到提高网络规划与管理的便捷性,减少网络扩展压力的目的,以满足同一张网络上不同业务的差异化需求。

Sea Turtle Foraging Optimization-Based Controller Placement with Blockchain-Assisted Intrusion Detection in Software-Defined Networks

Software-defined networking(SDN)algorithms are gaining increas-ing interest and are making networks flexible and agile.The basic idea of SDN is to move the control planes to more than one server’s named controllers and limit the data planes to numerous sending network components,enabling flexible and dynamic network management.A distinctive characteristic of SDN is that it can logically centralize the control plane by utilizing many physical controllers.The deployment of the controller—that is,the controller placement problem(CPP)—becomes a vital model challenge.Through the advancements of blockchain technology,data integrity between nodes can be enhanced with no requirement for a trusted third party.Using the lat-est developments in blockchain technology,this article designs a novel sea turtle foraging optimization algorithm for the controller placement problem(STFOA-CPP)with blockchain-based intrusion detection in an SDN environ-ment.The major intention of the STFOA-CPP technique is the maximization of lifetime,network connectivity,and load balancing with the minimization of latency.In addition,the STFOA-CPP technique is based on the sea turtles’food-searching characteristics of tracking the odour path of dimethyl sulphide(DMS)released from food sources.Moreover,the presented STFOA-CPP technique can adapt with the controller’s count mandated and the shift to controller mapping to variable network traffic.Finally,the blockchain can inspect the data integrity,determine significantly malicious input,and improve the robust nature of developing a trust relationship between sev-eral nodes in the SDN.To demonstrate the improved performance of the STFOA-CPP algorithm,a wide-ranging experimental analysis was carried out.The extensive comparison study highlighted the improved outcomes of the STFOA-CPP technique over other recent approaches.

长向量处理器高效RNN推理方法

模型深度的不断增加和处理序列长度的不一致对循环神经网络在不同处理器上的性能优化提出巨大挑战。针对自主研制的长向量处理器FT-M7032,实现了一个高效的循环神经网络加速引擎。该引擎采用行优先矩阵向量乘算法和数据感知的多核并行方式,提高矩阵向量乘的计算效率;采用两级内核融合优化方法降低临时数据传输的开销;采用手写汇编优化多种算子,进一步挖掘长向量处理器的性能潜力。实验表明,长向量处理器循环神经网络推理引擎可获得较高性能,相较于多核ARM CPU以及Intel Golden CPU,类循环神经网络模型长短记忆网络可获得最高62.68倍和3.12倍的性能加速。

NM-SpMM:面向国产异构向量处理器的半结构化稀疏矩阵乘算法

深度神经网络在自然语言处理、计算机视觉等领域取得了优异的成果,由于智能应用处理数据规模的增长和大模型的快速发展,对深度神经网络的推理性能要求越来越高,N∶M半结构化稀疏化技术成为平衡算力需求和应用效果的热点技术之一。国产异构向量处理器FT-M7032为智能模型处理中的数据并行和指令并行开发提供了较大空间。针对N∶M半结构化稀疏模型计算稀疏模式多样性,提出了一种面向FT-M7032的可灵活配置的稀疏矩阵乘算法NM-SpMM。NM-SpMM设计了一种高效的压缩偏移地址稀疏编码格式COA,避免了半结构化参数配置对稀疏数据访存计算的影响。基于COA编码,NM-SpMM对不同维度稀疏矩阵计算进行了细粒度优化。在FT-M7032单核上的实验结果表明,相较于稠密矩阵乘,NM-SpMM能获得1.73~21.00倍的加速,相较于采用CuSPARSE稀疏计算库的NVIDIA V100 GPU,能获得0.04~1.04倍的加速。

分布式高性能自组网节点技术研究

针对当前主流Mesh自组网技术节点传输带宽不足百兆,级跳数小于10的问题,提出采用多处理器构建实现分布式多跳、高带宽低时延的无线跳频的高性能自组网节点,对节点自动化组网连接、多信道选择避让、漫游切换及低时延高带宽网络多跳实现等关键技术进行研究实现。由测试结果分析可知,在20级跳内,文中节点组网带宽损失在30%以内且带宽保持在200 Mb/s以上,时延控制在100 ms内,可以满足现实应急场景下多终端智能硬件实时进行图像、视频等大数据量信息交互对高带宽低时延网络通信的需求。

基于NP的垃圾邮件分析系统的设计与实现

垃圾邮件的泛滥成灾给人们的正常生活带来了很大的不便和危害。该文设计并实现了基于NP的垃圾邮件分析系统,具有邮件抓取、还原和类别识别功能,能够有效识别垃圾邮件。实验结果表明,该系统对于垃圾邮件的追踪具有良好的实用价值。

一种基于PYNQ的神经网络加速系统

针对传统卷积神经网络计算复杂度高,耗时较长,难以应用到嵌入式移动端的问题,提出了一种以ZYNQ芯片作为主控的FPAG联合ARM实现的的神经网络加速系统。该系统的PL部分采用纯RTL开发,对卷积层的输入层和输出层进行了全并行化,对卷积窗口进行完全的展开,在一个时钟周期内可以同时完成81次乘法运算,同时对池化层和全连接层采用流水线的优化方式。相比常用的使用高层次综合工具进行优化的方法,该系统使用RTL语言从零开始设计卷积神经网络各个模块,进行了细粒度的优化,避免了冗余逻辑资源的产生,充分利用了片上资源。针对MINIST手写数字识别的网络模型,该系统的DSP利用率达到了95%,在100 MHz时钟频率下,硬件单帧图像处理时间仅为0.81 ms,功耗仅为1.601 W。

NP控制平面OS中基于分组属性的进程调度技术

在基于NP的网络处理系统中,存在各种各样的控制平面和数据平面交互信息。不同的信息分组具有不同的重要性,某些重要分组若得不到及时处理会导致系统和网络行为的紊乱,因此需要降低分组经历的时延,且越重要的分组经历的时延应该越小。从控制层面操作系统的角度来看,这要求分组处理进程的调度属性应该与所处理分组的属性关联起来。该文提出了一种基于分组属性的进程调度策略,给出了有关设计与实现。实验结果表明,该策略较好地达到了预期的目标。

电信企业NPS调研数据分析方法研究

随着社会经济快速发展,运营商面临的同质化竞争和来自互联网企业的异质化竞争愈发激烈。构建价值导向的NPS运营体系,切实提升价值客户的忠诚度,将成为驱动企业良性利润增长的关键点。以某地区NPS调研数据为样本,探索NPS数据的分析方法,首先采用主成分分析法深入挖掘NPS 3类用户对使用体验的关注点和差异,指导后续改进方向;其次采用贝叶斯网络进行用户行为建模分析,旨在寻找潜在价值用户。

NAPT-PT在NP-1c网络处理器上的实现

对EZchip公司NP-1c网络处理器进行研究,在熟悉其硬件体系结构和软件体系结构的基础上,设计和实现了一种高性能的协议转换网关。

数控机床工作台DSP定位误差系统设计及分析

为进一步优化数控机床对于测试误差的补偿功能,开发通过DSP硬件系统对误差进行准确预测并设置补偿措施。建立的定位误差模型预测补偿系统包含数控系统进给轴反馈结构、DSP建模预测系统以及数控系统。研究结果表明,采用Matlab软件运行得到的优化权值与阈值建立的GA-BP网络进行误差预测共需251μs;采用GA-BP网络构建的模型进行预测时达到了更高精度。该研究有助于提高数控机床加工精度,对提高加工参数的优化起到很好的指导意义以及控制效果。