Inductorless CMOS Low Noise Amplifier for Multiband Application in 0.1–1.2 GHz

A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range.

A wideband LNA employing gate-inductive-peaking and noise-canceling techniques in 0.18μm CMOS

This paper presents a wideband low noise amplifier （LNA） for multi-standard radio applications. The low noise characteristic is achieved by the noise-canceling technique while the bandwidth is enhanced by gate- inductive-peaking technique. High-frequency noise performance is consequently improved by the flattened gain over the entire operating frequency band. Fabricated in 0.18 μm CMOS process, the LNA achieves 2.5 GHz of -3 dB bandwidth and 16 dB of gain. The gain variation is within 4-0.8 dB from 300 MHz to 2.2 GHz. The measured noise figure （NF） and average IIP3 are 3.4 dB and -2 dBm, respectively. The proposed LNA occupies 0.39 mm2 core chip area. Operating at 1.8 V, the LNA drains a current of 11.7 mA.

Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

A CMOS RF（radio frequency） front-end for digital radio broadcasting applications is presented that contains a wideband LNA,I/Q-mixers and VGAs,supporting other various wireless communication standards in the ultrawide frequency band from 200 kHz to 2 GHz as well.Improvement of the NF（noise figure） and IP3（third-order intermodulation distortion） is attained without significant degradation of other performances like voltage gain and power consumption.The NF is minimized by noise-canceling technology,and the IP3 is improved by using differential multiple gate transistors（DMGTR）.The dB-in-linear VGA（variable gain amplifier） exploits a single PMOS to achieve exponential gain control.The circuit is fabricated in 0.18-μm CMOS technology.The S11 of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz.The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz.The DSB NF at maximum gain is 3.1-6.1 dB.The IIP3 at middle gain is -4.7 to 0.2 dBm.It consumes a DC power of only 36 mW at 1.8 V supply.

A fully integrated direct-conversion digital satellite tuner in 0.18μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented.A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end,while the synthesizer integrated the loop filter to reduce the solution cost and system debug time.Fabricated in 0.18μm CMOS,the chip achieves a less than 7.6 dB noise figure over a 900-2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is -91 dBm at the PCB connector.The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1℃integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

A novel low-noise linear-in-dB intermediate frequency variable-gain amplifier for DRM/DAB tuners

A broadband CMOS intermediate frequency （IF） variable-gain amplifier （VGA） for DRM/DAB tuners is presented. The VGA comprises two cascaded stages： one is for noise-canceling and another is for signal-summing. The chip is fabricated in a standard 0.18μm 1P6M RF CMOS process of SMIC. Measured results show a good linear-in-dB gain characteristic in 28 dB dynamic gain range of-10 to 18 dB. It can operate in the frequency range of 30-700 MHz and consumes 27 mW at 1.8 V supply with the on-chip test buffer. The minimum noise figure is only 3.1 dB at maximum gain and the input-referred 1 dB gain compression point at the minimum gain is -3.9 dBm.