DIGITAL BACKGROUND CALIBRATION OF CAPACITOR MISMATCHES AND HARMONIC DISTORTION IN PIPELINED ADC

A correlation-based digital background calibration algorithm for pipelined Analog-to- Digital Converters (ADCs) is presented in this paper. The merit of the calibration algorithm is that the main errors information, which include the capacitor mismatches and residue amplifier distortion, are extracted integrally. A modified 1st pipelined stage is adopted to solve the signal overflow caused by the Pseudo-random Noise (PN) sequences. Behavioral simulation results verify the effectiveness of the algorithm. It improves the Signal-to-Noise-plus-Distortion Ratio (SNDR) and Spurious-Free-Dynamic-Range (SFDR) of the pipelined ADC from 41.8 dB to 78.3 dB and 55.6 dB to 98.6 dB, respectively, which is comparable to the prior arts.

Sequence Length Limits for Controlling False Positives in Discovering Nucleotide Sequence Motifs

In the study of motif discovery, especially the transcription factor DNA binding sites discovery, a too long input sequence would return non-informative motifs rather than those biological functional motifs. This paper gave theoretical analyses and computational experiments to suggest the length limits of the input sequence. When the sequence length exceeds a certain critical point, the probability of discovering the motif decreases sharply. The work not only gave an explanation on the unsatisfying results of the existed motif discovery problems that the input sequence length might be too long and exceed the point, but also provided an estimation of input sequence length we should accept to get more meaningful and reliable results in motif discovery.

All-optical pseudo noise sequence generator using a micro-ring resonator

A scheme for the generation of a pseudo noise(PN)sequence in the optical domain is proposed.The cascaded units of micro-ring resonator(MRR)-based D flip-flop are used to design the device.D flip-flops consist of a single MRR and share the same optical pump signal.Numerical analysis is performed,and simulated results are discussed.The proposed device can be used as a building block for optical computing and for creating an information processing system.

A robust and simple two-mode digital calibration technique for pipelined ADC

This paper presents a two-mode digital calibration technique for pipelined analog-to-digital converters （ADC）.The proposed calibration eliminates the errors of residual difference voltage induced by capacitor mismatch of pseudorandom（PN） sequence injection capacitors at the ADC initialization,while applies digital background calibration to continuously compensate the interstage gain errors in ADC normal operation.The presented technique not only reduces the complexity of analog circuit by eliminating the implementation of PN sequence with accurate amplitude in analog domain,but also improves the performance of digital background calibration by minimizing the sensitivity of calibration accuracy to sub-ADC errors.The use of opamps with low DC gains in normal operation makes the proposed design more compatible with future nanometer CMOS technology.The prototype of a 12-bit 40-MS/s pipelined ADC with the two-mode digital calibration is implemented in 0.18-μm CMOS process.Adopting a simple telescopic opamp with a DC gain of 58-dB in the first stage,the measured SFDR and SNDR within the first Nyquist zone reach 80-dB and 66-dB,respectively.With the calibration,the maximum integral nonlinearity （INL） of the ADC reduces from 4.75-LSB to 0.65-LSB,while the ADC core consumes 82-mW at 3.3-V power supply.