C-CORE:Clustering by Code Representation to Prioritize Test Cases in Compiler Testing

Edge devices,due to their limited computational and storage resources,often require the use of compilers for program optimization.Therefore,ensuring the security and reliability of these compilers is of paramount importance in the emerging field of edge AI.One widely used testing method for this purpose is fuzz testing,which detects bugs by inputting random test cases into the target program.However,this process consumes significant time and resources.To improve the efficiency of compiler fuzz testing,it is common practice to utilize test case prioritization techniques.Some researchers use machine learning to predict the code coverage of test cases,aiming to maximize the test capability for the target compiler by increasing the overall predicted coverage of the test cases.Nevertheless,these methods can only forecast the code coverage of the compiler at a specific optimization level,potentially missing many optimization-related bugs.In this paper,we introduce C-CORE(short for Clustering by Code Representation),the first framework to prioritize test cases according to their code representations,which are derived directly from the source codes.This approach avoids being limited to specific compiler states and extends to a broader range of compiler bugs.Specifically,we first train a scaled pre-trained programming language model to capture as many common features as possible from the test cases generated by a fuzzer.Using this pre-trained model,we then train two downstream models:one for predicting the likelihood of triggering a bug and another for identifying code representations associated with bugs.Subsequently,we cluster the test cases according to their code representations and select the highest-scoring test case from each cluster as the high-quality test case.This reduction in redundant testing cases leads to time savings.Comprehensive evaluation results reveal that code representations are better at distinguishing test capabilities,and C-CORE significantly enhances testing efficiency.Across four datasets,C-CORE increases the average of the percentage of faults detected(APFD)value by 0.16 to 0.31 and reduces test time by over 50% in 46% of cases.When compared to the best results from approaches using predicted code coverage,C-CORE improves the APFD value by 1.1% to 12.3% and achieves an overall time-saving of 159.1%.

Algorithms for Pre-Compiling Programs by Parallel Compilers

The paper addresses the challenge of transmitting a big number offiles stored in a data center(DC),encrypting them by compilers,and sending them through a network at an acceptable time.Face to the big number offiles,only one compiler may not be sufficient to encrypt data in an acceptable time.In this paper,we consider the problem of several compilers and the objective is tofind an algorithm that can give an efficient schedule for the givenfiles to be compiled by the compilers.The main objective of the work is to minimize the gap in the total size of assignedfiles between compilers.This minimization ensures the fair distribution offiles to different compilers.This problem is considered to be a very hard problem.This paper presents two research axes.Thefirst axis is related to architecture.We propose a novel pre-compiler architecture in this context.The second axis is algorithmic development.We develop six algorithms to solve the problem,in this context.These algorithms are based on the dispatching rules method,decomposition method,and an iterative approach.These algorithms give approximate solutions for the studied problem.An experimental result is imple-mented to show the performance of algorithms.Several indicators are used to measure the performance of the proposed algorithms.In addition,five classes are proposed to test the algorithms with a total of 2350 instances.A comparison between the proposed algorithms is presented in different tables discussed to show the performance of each algorithm.The result showed that the best algorithm is the Iterative-mixed Smallest-Longest-Heuristic(ISL)with a percentage equal to 97.7%and an average running time equal to 0.148 s.All other algorithms did not exceed 22%as a percentage.The best algorithm excluding ISL is Iterative-mixed Longest-Smallest Heuristic(ILS)with a percentage equal to 21,4%and an average running time equal to 0.150 s.

Constructing an AI Compiler for ARM Cortex-M Devices

The diversity of software and hardware forces programmers to spend a great deal of time optimizing their source code,which often requires specific treatment for each platform.The problem becomes critical on embedded devices,where computational and memory resources are strictly constrained.Compilers play an essential role in deploying source code on a target device through the backend.In this work,a novel backend for the Open Neural Network Compiler(ONNC)is proposed,which exploits machine learning to optimize code for the ARM Cortex-M device.The backend requires minimal changes to Open Neural Network Exchange(ONNX)models.Several novel optimization techniques are also incorporated in the backend,such as quantizing the ONNX model’s weight and automatically tuning the dimensions of operators in computations.The performance of the proposed framework is evaluated for two applications:handwritten digit recognition on the Modified National Institute of Standards and Technology(MNIST)dataset and model,and image classification on the Canadian Institute For Advanced Research and 10(CIFAR-10)dataset with the AlexNet-Light model.The system achieves 98.90%and 90.55%accuracy for handwritten digit recognition and image classification,respectively.Furthermore,the proposed architecture is significantly more lightweight than other state-of-theart models in terms of both computation time and generated source code complexity.From the system perspective,this work provides a novel approach to deploying direct computations from the available ONNX models to target devices by optimizing compilers while maintaining high efficiency in accuracy performance.

面向VHDL语言编译器VCompiler93的研制

研制用于 VHDL语言的编译器 ,语法分析采用一便扫描和预测分析的策略 ,提出了适用于处理 VHDL语言中语法冲突、各类重载语法、静态层次确立等语法现象的具体算法 .开发出面向 VHDL93标准的 VHDL语言编译器 VCompiler93,该编译器运行正常 ,表明所采用的解决方案合理 ,算法有效 .

IDL Compiler API Design, Application and Validation Based on XML API

In order to adapt different languages and platforms, the paper discusses how to process and validate IDL symbol table and intermediate code by XML API. It puts emphasis on IDL AP1 extension towards DOM API based on the idea of combining XML with IDL compilers. At last, the IDL compiler designing framework based on XML AP! is given, in which compiler front end can be managed and validated by some XML techniques and tools, IDL API can be validated on the basis of test, so IDL intermediate code is provided with maintainability, portability and generation. IDL compiler can be developed and extended by XML-based API, which realizes versatility and portability of modern compiler.

Microsphere femtosecond laser sub-50 nm structuring in far field via non-linear absorption

Creation of arbitrary features with high resolution is critically important in the fabrication of nano-optoelectronic devices.Here,sub-50 nm surface structuring is achieved directly on Sb2S3 thin films via microsphere femtosecond laser irradi-ation in far field.By varying laser fluence and scanning speed,nano-feature sizes can be flexibly tuned.Such small patterns are attributed to the co-effect of microsphere focusing,two-photons absorption,top threshold effect,and high-repetition-rate femtosecond laser-induced incubation effect.The minimum feature size can be reduced down to~30 nm(λ/26)by manipulating film thickness.The fitting analysis between the ablation width and depth predicts that the feature size can be down to~15 nm at the film thickness of~10 nm.A nano-grating is fabricated,which demonstrates desirable beam diffraction performance.This nano-scale resolution would be highly attractive for next-generation laser nano-lithography in far field and in ambient air.

A High Speed Signal Processing Machine -Its Architecture, Language and Compiler

A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.

The Implementation of the ASN.1-C++ Compiler and Its Application in IN

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AN OBJECT ORIENTED C++ PARALLEL COMPILER SYSTEM

An object-oriented C++ parallel compiler System, called OOCPCS, is developed to facilitate programmers to write sequential programs using C++ or Annotated C++ language for parallel computahon. OOCPCS bases on an integrated object-oriented paradigm and large-grain data flow model, called OOLGDFM, and recognizes automatically parallel objects using parallel compiling techniques. The paper describes the object-oriented parallel model and realization of the System on networks.

Constructing a Simple Verbal Compiler

The paper’s purpose is to design and program the four operation-calculators that receives voice instructions and runs them as either a voice or text phase. The Calculator simulates the work of the Compiler. The paper is a practical example programmed to support that it is possible to construct a verbal Compiler.

Compiler IR-Based Program Encoding Method for Software Defect Prediction

With the continuous expansion of software applications,people’s requirements for software quality are increasing.Software defect prediction is an important technology to improve software quality.It often encodes the software into several features and applies the machine learning method to build defect prediction classifiers,which can estimate the software areas is clean or buggy.However,the current encoding methods are mainly based on the traditional manual features or the AST of source code.Traditional manual features are difficult to reflect the deep semantics of programs,and there is a lot of noise information in AST,which affects the expression of semantic features.To overcome the above deficiencies,we combined with the Convolutional Neural Networks(CNN)and proposed a novel compiler Intermediate Representation(IR)based program encoding method for software defect prediction(CIR-CNN).Specifically,our program encoding method is based on the compiler IR,which can eliminate a large amount of noise information in the syntax structure of the source code and facilitate the acquisition of more accurate semantic information.Secondly,with the help of data flow analysis,a Data Dependency Graph(DDG)is constructed on the compiler IR,which helps to capture the deeper semantic information of the program.Finally,we use the widely used CNN model to build a software defect prediction model,which can increase the adaptive ability of the method.To evaluate the performance of the CIR-CNN,we use seven projects from PROMISE datasets to set up comparative experiments.The experiments results show that,in WPDP,with our CIR-CNN method,the prediction accuracy was improved by 12%for the AST-encoded CNN-based model and by 20.9%for the traditional features-based LR model,respectively.And in CPDP,the AST-encoded DBNbased model was improved by 9.1%and the traditional features-based TCA+model by 19.2%,respectively.

Stochastic Models to Mitigate Sparse Sensor Attacks in Continuous-Time Non-Linear Cyber-Physical Systems

Cyber-Physical Systems are very vulnerable to sparse sensor attacks.But current protection mechanisms employ linear and deterministic models which cannot detect attacks precisely.Therefore,in this paper,we propose a new non-linear generalized model to describe Cyber-Physical Systems.This model includes unknown multivariable discrete and continuous-time functions and different multiplicative noises to represent the evolution of physical processes and randomeffects in the physical and computationalworlds.Besides,the digitalization stage in hardware devices is represented too.Attackers and most critical sparse sensor attacks are described through a stochastic process.The reconstruction and protectionmechanisms are based on aweighted stochasticmodel.Error probability in data samples is estimated through different indicators commonly employed in non-linear dynamics(such as the Fourier transform,first-return maps,or the probability density function).A decision algorithm calculates the final reconstructed value considering the previous error probability.An experimental validation based on simulation tools and real deployments is also carried out.Both,the new technology performance and scalability are studied.Results prove that the proposed solution protects Cyber-Physical Systems against up to 92%of attacks and perturbations,with a computational delay below 2.5 s.The proposed model shows a linear complexity,as recursive or iterative structures are not employed,just algebraic and probabilistic functions.In conclusion,the new model and reconstructionmechanism can protect successfully Cyber-Physical Systems against sparse sensor attacks,even in dense or pervasive deployments and scenarios.

高性能计算与标准化的完美结合——Intel Compiler 8.0及其配套工具介绍

在x86体系结构的PC里,编译代码质量最好的C++是谁,不是VC++,不是Borland C++,也不是g++,而是InterC++。本文将带你畅游这个高性能编译器的世界。体会一下无需修改程序就可提升20％性能的美妙感觉。

THE DESIGN AND IMPLEMENTATION OF B96 COMPILER AND B96/8096/8098 SOFTWARE EMULATING PLATFORM IDDEE

A new high-level langusge,B96,which is compiling-type and MCS-96 single chip computer series oriented ,has recently been designed and implemented by the authors. This paper discusses its design thought and its implementation. The paper also accounts for the design of B96/8096/8098 IDDEE,a software Integrated Debugging & Developing Environment of Emulation,which is used to debug and develop 8096/8098 assemble language and/or B96 high-level language source program on PC-based emulating platform.

The Existence of Meromorphic Solutions to Non-Linear Delay Differential Equations

In this paper, we study the existence of the transcendental meromorphic solution of the delay differential equations , where a(z) is a rational function, and are polynomials in w(z) with rational coefficients, k is a positive integer. Under the assumption when above equations own transcendental meromorphic solutions with minimal hyper-type, we derive the concrete conditions on the degree of the right side of them. Specially, when w(z)=0 is a root of , its multiplicity is at most k. Some examples are given here to illustrate that our results are accurate.

新工科背景下编译原理教学改革研究

该文剖释传统编译原理教育教学的缺陷,指出为适应计算机人才能力培养和行业需求,在新工科背景下,面向OBE理念,突出交叉融合,充分利用多种教学平台和教学软件,融合案例教学、启发引导、项目驱动和翻转课堂等教学方法进行线上、线下混合教学。培养学生使用编译知识来解决复杂工程问题的能力和主动学习意识,提高课程教学质量,促使学生专业、素质全面发展。

中国医院协会《中国医院质量安全管理》团体标准编制与应用实践研究

中国医院协会以医疗质量安全为主题,组织开展《中国医院质量安全管理》系列团体标准编制与应用建设。文章从标准建设背景、编制特点、应用模式等方面进行阐释,并对编制中的问题进行探讨,提出提高团体标准质量及扩展应用路径和方式,充分发挥团体标准作用和价值等思考。