利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率...利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。展开更多
采用半导体光放大器 (SemiconductorOpticalAmplifier,SOA)的分段模型 ,对基于SOA光纤环镜的非归零 (Non Return to Zero ,NRZ)信号时钟分量提取进行了数值模拟 SOA光纤环镜可以将NRZ信号转化为包含其时钟分量的伪归零 (Pseudo Return ...采用半导体光放大器 (SemiconductorOpticalAmplifier,SOA)的分段模型 ,对基于SOA光纤环镜的非归零 (Non Return to Zero ,NRZ)信号时钟分量提取进行了数值模拟 SOA光纤环镜可以将NRZ信号转化为包含其时钟分量的伪归零 (Pseudo Return to Zero ,PRZ)信号 给出了2 .5Gb/s下的模拟计算结果 ,并与实验结果进行了比较 ,进一步给出了展开更多
This paper presents the design and testing of a 15 Gbps non-return-to-zero(NRZ),30 Gbps 4-level pulse amplitude modulation(PAM4)configurable laser diode driver(LDD)implemented in 0.15-μm GaAs E-mode pHEMT technology....This paper presents the design and testing of a 15 Gbps non-return-to-zero(NRZ),30 Gbps 4-level pulse amplitude modulation(PAM4)configurable laser diode driver(LDD)implemented in 0.15-μm GaAs E-mode pHEMT technology.The driver bandwidth is enhanced by utilizing cross-coupled neutralization capacitors across the output stage.The output transmission-line back-termination,which absorbs signal reflections from the imperfectly matched load,is performed passively with on-chip 50-Ωresistors.The proposed 30 Gbps PAM4 LDD is implemented by combining two 15 Gbps-NRZ LDDs,as the high and low amplification paths,to generate PAM4 output current signal with levels of 0,40,80,and 120 mA when driving 25-Ωlasers.The high and low amplification paths can be used separately or simultaneously as a 15 Gbps-NRZ LDD.The measurement results show clear output eye diagrams at speeds of up to 15 and 30 Gbps for the NRZ and PAM4 drivers,respectively.At a maximum output current of 120 mA,the driver consumes 1.228 W from a single supply voltage of-5.2 V.The proposed driver shows a high current driving capability with a better output power to power dissipation ratio,which makes it suitable for driving high current distributed feedback(DFB)lasers.The chip occupies a total area of 0.7×1.3 mm^(2).展开更多
文摘利用法国OMM IC公司的0.2μm G aA s PHEM T工艺,设计实现了10 G b/s NRZ码时钟信息提取电路。该电路采用改进型双平衡G ilbert单元的结构,引进了容性源极耦合差动电流放大器和调谐负载电路,大大提高了电路的性能。测试表明:在输入速率为9.953 28 G b/s长度为223-1伪随机序列的情况下,提取出的时钟的均方根抖动是1.18 ps,峰峰值抖动是8.44 ps。芯片面积为0.5 mm×1 mm,采用-5 V电源供电,功耗约为100 mW。
文摘采用半导体光放大器 (SemiconductorOpticalAmplifier,SOA)的分段模型 ,对基于SOA光纤环镜的非归零 (Non Return to Zero ,NRZ)信号时钟分量提取进行了数值模拟 SOA光纤环镜可以将NRZ信号转化为包含其时钟分量的伪归零 (Pseudo Return to Zero ,PRZ)信号 给出了2 .5Gb/s下的模拟计算结果 ,并与实验结果进行了比较 ,进一步给出了
文摘This paper presents the design and testing of a 15 Gbps non-return-to-zero(NRZ),30 Gbps 4-level pulse amplitude modulation(PAM4)configurable laser diode driver(LDD)implemented in 0.15-μm GaAs E-mode pHEMT technology.The driver bandwidth is enhanced by utilizing cross-coupled neutralization capacitors across the output stage.The output transmission-line back-termination,which absorbs signal reflections from the imperfectly matched load,is performed passively with on-chip 50-Ωresistors.The proposed 30 Gbps PAM4 LDD is implemented by combining two 15 Gbps-NRZ LDDs,as the high and low amplification paths,to generate PAM4 output current signal with levels of 0,40,80,and 120 mA when driving 25-Ωlasers.The high and low amplification paths can be used separately or simultaneously as a 15 Gbps-NRZ LDD.The measurement results show clear output eye diagrams at speeds of up to 15 and 30 Gbps for the NRZ and PAM4 drivers,respectively.At a maximum output current of 120 mA,the driver consumes 1.228 W from a single supply voltage of-5.2 V.The proposed driver shows a high current driving capability with a better output power to power dissipation ratio,which makes it suitable for driving high current distributed feedback(DFB)lasers.The chip occupies a total area of 0.7×1.3 mm^(2).
