Overview of one transistor type of hybrid organic ferroelectric non-volatile memory

Organic ferroelectric memory devices based on field effect transistors that can be configured between two stable states of on and off have been widely researched as the next generation data storage media in recent years.This emerging type of memory devices can lead to a new instrument system as a potential alternative to previous non-volatile memory building blocks in future processing units because of their numerous merits such as cost-effective process,simple structure and freedom in substrate choices.This bi-stable non-volatile memory device of information storage has been investigated using several organic or inorganic semiconductors with organic ferroelectric polymer materials.Recent progresses in this ferroelectric memory field,hybrid system have attracted a lot of attention due to their excellent device performance in comparison with that of all organic systems.In this paper,a general review of this type of ferroelectric non-volatile memory is provided,which include the device structure,organic ferroelectric materials,electrical characteristics and working principles.We also present some snapshots of our previous study on hybrid ferroelectric memories including our recent work based on zinc oxide nanowire channels.

Fabrication and integration of photonic devices for phase-change memory and neuromorphic computing

In the past decade,there has been tremendous progress in integrating chalcogenide phase-change materials(PCMs)on the silicon photonic platform for non-volatile memory to neuromorphic in-memory computing applications.In particular,these non von Neumann computational elements and systems benefit from mass manufacturing of silicon photonic integrated circuits(PICs)on 8-inch wafers using a 130 nm complementary metal-oxide semiconductor line.Chip manufacturing based on deep-ultraviolet lithography and electron-beam lithography enables rapid prototyping of PICs,which can be integrated with high-quality PCMs based on the wafer-scale sputtering technique as a back-end-of-line process.In this article,we present an overview of recent advances in waveguide integrated PCM memory cells,functional devices,and neuromorphic systems,with an emphasis on fabrication and integration processes to attain state-of-the-art device performance.After a short overview of PCM based photonic devices,we discuss the materials properties of the functional layer as well as the progress on the light guiding layer,namely,the silicon and germanium waveguide platforms.Next,we discuss the cleanroom fabrication flow of waveguide devices integrated with thin films and nanowires,silicon waveguides and plasmonic microheaters for the electrothermal switching of PCMs and mixed-mode operation.Finally,the fabrication of photonic and photonic–electronic neuromorphic computing systems is reviewed.These systems consist of arrays of PCM memory elements for associative learning,matrix-vector multiplication,and pattern recognition.With large-scale integration,the neuromorphic photonic computing paradigm holds the promise to outperform digital electronic accelerators by taking the advantages of ultra-high bandwidth,high speed,and energy-efficient operation in running machine learning algorithms.

Formation of high density TiN nanocrystals and its application in non-volatile memories

Non-volatile memory based on TiN nanocrystal （TiN-NC） charge storage nodes embedded in SiO2 has been fabricated and its electrical properties have been measured. It was found that the density and size distribution of TiN-NCs can be controlled by annealing temperature. The formation of well separated crystalline TiN nano-dots with an average size of 5 nm is confirmed by transmission electron microscopy and x-ray diffraction, x-ray photoelectron spectroscopy confirms the existence of a transition layer of TiNxOy/SiON oxide between TiN-NC and SiO2, which reduces the barrier height of tunnel oxide and thereby enhances programming/erasing speed. The memory device shows a memory window of 2.5V and an endurance cycle throughout 10^5. Its charging mechanism, which is interpreted from the analysis of programming speed （dVth/dt） and the gate leakage versus voltage characteristics （Ig vs Vg）, has been explained by direct tunnelling for tunnel oxide and Fowler Nordheim tunnelling for control oxide at programming voltages lower than 9V, and by Fowler-Nordheim tunnelling for both the oxides at programming voltages higher than 9V.

Molecular dynamics simulations on the wet/dry self-latching and electric fields triggered wet/dry transitions between nanosheets:A non-volatile memory nanostructure

We design a nanostructure composing of two nanoscale graphene sheets parallelly immersed in water.Using molecular dynamics simulations,we demonstrate that the wet/dry state between the graphene sheets can be self-latched;moreover,the wet→dry/dry→wet transition takes place when applying an external electric field perpendicular/parallel to the graphene sheets(E;/E;).This structure works like a flash memory device(a non-volatile memory):the stored information(wet and dry states)of the system can be kept spontaneously,and can also be rewritten by external electric fields.On the one hand,when the distance between the two nanosheets is close to a certain distance,the free energy barriers for the transitions dry→wet and wet→dry can be quite large.As a result,the wet and dry states are self-latched.On the other hand,an E;and an E;will respectively increase and decrease the free energy of the water located in-between the two nanosheets.Consequently,the wet→dry and dry→wet transitions are observed.Our results may be useful for designing novel information memory devices.

An Overview of Non-Volatile Flip-Flops Based on Emerging Memory Technologies(Invited paper)

Low power consumption is a major issue in nowadays electronics systems. This trend is pushed by the development of data center related to cloud services and soon to the Internet of Things （IoT） deployment. Memories are one of the major contributors to power consumption. However, the development of emerging memory technologies paves the way to low-power design, through the partial replacement of the dynamic random access memory （DRAM） with the non-volatile stand-alone memory in servers or with the embedded or distributed emerging non-volatile memory in IoT objects. In the latter case, non-volatile flip-flops （NVFFs） seem a promising candidate to replace the retention latch. Indeed, IoT objects present long sleep time and NVFFs offer to save data in registers with zero power when the application is idle. This paper gives an overview of NVFF architecture flavors for various emerging memory technologies.

Design of an Electrically Written and Optically Read Non-volatile Memory Device Employing BiFeO3/Au Heterostructures with Strong Absorption Resonance

Exploiting new concepts for dense, fast, and nonvolatile random access memory with reduced energy consump- tion is a significant issue for information technology. Here we design an ＇electrically written and optically read＇ information storage device employing BiFeO3/A u heterostruetures with strong absorption resonance. The electro- optic effect is the basis for the device design, which arises from the strong absorption resonance in BiFeO3/Au heterostructures and the electrically tunable significant birefringence of the BiFeO3 film. We first construct a sim- ulation calculation of the BiFeO3/Au structure spectrum and identify absorption resonance and electro-optical modulation characteristics. Following a micro scale partition, the surface reflected light intensity of different polarization units is calculated. The results depend on electric polarization states of the BiFeO3 film, thus BiFeO3/Au heterostructures can essentially be designed as a type of electrically written and optically read infor- mation storage device by utilizing the scanning near-field optical microscopy technology based on the conductive silicon cantilever tip with nanofabricated aperture. This work will shed light on information storage technology.

Approximate Similarity-Aware Compression for Non-Volatile Main Memory

Image bitmaps,i.e.,data containing pixels and visual perception,have been widely used in emerging applica-tions for pixel operations while consuming lots of memory space and energy.Compared with legacy DRAM(dynamic ran-dom access memory),non-volatile memories(NVMs)are suitable for bitmap storage due to the salient features of high density and intrinsic durability.However,writing NVMs suffers from higher energy consumption and latency compared with read accesses.Existing precise or approximate compression schemes in NVM controllers show limited performance for bitmaps due to the irregular data patterns and variance in bitmaps.We observe the pixel-level similarity when writing bitmaps due to the analogous contents in adjacent pixels.By exploiting the pixel-level similarity,we propose SimCom,an approximate similarity-aware compression scheme in the NVM module controller,to efficiently compress data for each write access on-the-fly.The idea behind SimCom is to compress continuous similar words into the pairs of base words with runs.The storage costs for small runs are further mitigated by reusing the least significant bits of base words.SimCom adaptively selects an appropriate compression mode for various bitmap formats,thus achieving an efficient trade-off be-tween quality and memory performance.We implement SimCom on GEM5/zsim with NVMain and evaluate the perfor-mance with real-world image/video workloads.Our results demonstrate the efficacy and efficiency of our SimCom with an efficient quality-performance trade-off.

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition.The battery life is the critical problem for wearable devices. The non-volatile memory(NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption,NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory(DRAM). In this paper, we assume to use hybrid random access memory(RAM)and NVM architecture for the smart bracelet system.This paper presents a data management algorithm named bracelet power-aware data management(BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.

BOOM-KV:基于RDMA的高性能NVM键值数据库

随着英特尔傲腾数据中心持久化内存模块(DCPMM)开始进入市场以及远程直接内存访问(RDMA)硬件成本的降低,设计融合非易失性内存(NVM)和RDMA的键值(KV)数据库面临新的机遇和挑战。构建基于NVM和RDMA的KV数据库的关键在于设计一个高效的通信协议。遗憾的是,现有工作或采用NVM不感知的RDMA协议,或采用低效的NVM感知的RDMA协议,这导致它们无法最大化KV数据库的性能。本文提出了BOOM协议——一种新型的NVM感知的RDMA协议。相较于NVM不感知的协议,BOOM协议允许直接对远端NVM进行RDMA操作,消除了冗余的数据拷贝;相较于现有的NVM感知的协议,它可以显著减少元数据请求,降低KV请求的端对端延迟。在BOOM协议的基础上构建了BOOM-KV,并针对服务端中央处理器(CPU)利用率和宕机持久化等问题进一步进行优化。将BOOM-KV与最新的研究成果进行对比,结果表明,BOOM-KV能显著降低请求延迟,其中PUT延迟最大降低了42%,GET延迟最大降低了41%,并且展现出良好的扩展性。

基于非易失性内存的知识图谱系统优化研究

分布式系统的高扩展性和高可用性使得在其上构建大规模知识图谱已经成为产业发展趋势。新兴的分布式图数据库更推崇采用NoSQL等数据模型,如键值存储作为其存储引擎,以进一步提高其可扩展性和实用性。在这种情况下,上层的图查询语言的语句会被翻译成一组混合的键值操作。为了加速查询翻译生成的键值操作,提出了基于非易失性内存查询性能加速(knowledge graph booster,KGB)的知识图谱系统。KGB主要包含面向邻域查询加速的NVM辅助索引,用于降低键值存储的读取成本;快速响应的改进Raft算法,用于实现高效的键值存取操作;以及面向键值存储引擎的调优机制,为知识图谱存储系统获得额外的性能提升。通过实验表明,KGB能有效降低知识图谱系统的平均延迟和尾延迟的影响,实现更高的性能提升。

用于通用存储和神经形态计算的相变存储器的研究进展

存算一体技术目前被认为是一种可以消除冯·诺依曼计算架构瓶颈的可行性技术。在众多的存算一体器件中,相变存储器(PCM)因其具有非易失性、可微缩性、高开关速度、低操作电压、循环寿命长以及与现有半导体工艺相兼容等优点,被认为是未来通用存储和神经形态计算器件中最具竞争力的候选者之一。首先介绍了PCM的工作原理和器件材料结构,并详细讨论了PCM在通用存储和神经形态计算领域的应用。PCM具有高集成度和低功耗的共性需求,但这两个应用领域对材料性能有不同的侧重点。详细分析了PCM目前存在的优缺点,如高编程电流导致的功耗问题,以及商业化应用面临的主要挑战。最后,针对PCM的研究现状提出了一系列改进措施,包括材料选择、器件结构设计、预操作、热损耗降低、3D架构,以及解决阻态漂移等问题,以推动其进一步发展和应用。

支持高并发访问的新型NVM存储系统

I/O系统软件栈是影响NVM存储系统性能的重要因素。针对NVM存储系统的读写速度不均衡、写寿命有限等问题,设计了同异步融合的访问请求管理策略;在使用异步策略管理数据量较大的写操作的同时,仍然使用同步策略管理读请求和少量数据的写请求。针对多核处理器环境下不同计算核心访问存储系统时地址转换开销大的问题,设计了面向多核处理器地址转换缓存策略,减少地址转换的时间开销。最后实现了支持高并发访问NVM存储系统(CNVMS)的原型,并使用通用测试工具进行了随机读写、顺序读写、混合读写和实际应用负载的测试。实验结果表明,与PMBD相比,所提策略能提高1%～22%的读写速度和9%～15%的IOPS,验证了CNVMS策略能有效提高NVM存储系统的I/O性能和访问请求处理速度。

内存高效的持久性分布式文件系统客户端缓存DFS-Cache

为了在数据密集型工作流下有效降低缓存碎片整理开销并提高缓存命中率,提出一种持久性分布式文件系统客户端缓存DFS-Cache(Distributed File System Cache)。DFS-Cache基于非易失性内存(NVM)设计实现,能够保证数据的持久性和崩溃一致性,并大幅减少冷启动时间。DFS-Cache包括基于虚拟内存重映射的缓存碎片整理机制和基于生存时间(TTL)的缓存空间管理策略。前者基于NVM可被内存控制器直接寻址的特性,动态修改虚拟地址和物理地址之间的映射关系,实现零拷贝的内存碎片整理;后者是一种冷热分离的分组管理策略,借助重映射的缓存碎片整理机制,提升缓存空间的管理效率。实验采用真实的Intel傲腾持久性内存设备,对比商用的分布式文件系统MooseFS和GlusterFS,采用Fio和Filebench等标准测试程序,DFS-Cache最高能提升5.73倍和1.89倍的系统吞吐量。

Chalcogenide Ovonic Threshold Switching Selector

Today’s explosion of data urgently requires memory technologies capable of storing large volumes of data in shorter time frames,a feat unattain-able with Flash or DRAM.Intel Optane,commonly referred to as three-dimensional phase change memory,stands out as one of the most promising candidates.The Optane with cross-point architecture is constructed through layering a storage element and a selector known as the ovonic threshold switch(OTS).The OTS device,which employs chalcogenide film,has thereby gathered increased attention in recent years.In this paper,we begin by providing a brief introduction to the discovery process of the OTS phenomenon.Subsequently,we summarize the key elec-trical parameters of OTS devices and delve into recent explorations of OTS materials,which are categorized as Se-based,Te-based,and S-based material systems.Furthermore,we discuss various models for the OTS switching mechanism,including field-induced nucleation model,as well as several carrier injection models.Additionally,we review the progress and innovations in OTS mechanism research.Finally,we highlight the successful application of OTS devices in three-dimensional high-density memory and offer insights into their promising performance and extensive prospects in emerging applications,such as self-selecting memory and neuromorphic computing.

嵌入式Flash Memory Cell技术

本文分析了目前常用的快闪存储器(Flash Memory)存储单元结构,介绍了一种适用于嵌入的单元结构,存储器阵列设计、可靠性设计技术。

NEHASH:high-concurrency extendible hashing for non-volatile memory

Extendible hashing is an effective way to manage increasingly large file system metadata,but it suffers from low concurrency and lack of optimization for non-volatile memory(NVM).In this paper,a multilevel hash directory based on lazy expansion is designed to improve the concurrency and efficiency of extendible hashing,and a hash bucket management algorithm based on groups is presented to improve the efficiency of hash key management by reducing the size of the hash bucket,thereby improving the performance of extendible hashing.Meanwhile,a hierarchical storage strategy of extendible hashing for NVM is given to take advantage of dynamic random access memory(DRAM)and NVM.Furthermore,on the basis of the device driver for Intel Optane DC Persistent Memory,the prototype of high-concurrency extendible hashing named NEHASH is implemented.Yahoo cloud serving benchmark(YCSB)is used to test and compare with CCEH,level hashing,and cuckoo hashing.The results show that NEHASH can improve read throughput by up to 16.5%and write throughput by 19.3%.

一种支持大页的层次化DRAM/NVM混合内存系统

随着大数据应用的涌现,计算机系统需要更大容量的内存以满足大数据处理的高时效性需求.新型非易失性存储器(non-volatile memory,NVM)结合传统动态随机存储器(dynamic random access memory,DRAM)组成的混合内存系统具有内存容量大、功耗低的优势,因而得到了广泛关注.大数据应用同时也面临着旁路转换缓冲器(translation lookaside buffer,TLB)缺失率过高的性能瓶颈.大页可以有效降低TLB缺失率,然而,在混合内存中支持大页面临着大页迁移开销过大的问题.因此,设计了一种支持大页和大容量缓存的层次化混合内存系统:DRAM和NVM分别使用4KB和2MB粒度的页面分别进行管理,同时在DRAM和NVM之间实现直接映射.设计了基于访存频率的DRAM缓存数据过滤机制,减轻了带宽压力.提出了基于内存实时信息的动态热度阈值调整策略,灵活适应应用访存特征的变化.实验显示:与使用大页的全NVM内存系统和缓存热页(caching hot page,CHOP)系统相比平均有69.9%和15.2%的性能提升,而与使用大页的全DRAM内存系统相比平均只有8.8%的性能差距.

基于高性能SOC FPGA阵列的NVM验证架构设计与验证

新型非易失性存储器(non-volatile memory,NVM)技术日渐成熟,延迟越来越低,带宽越来越高,未来将不仅有可能取代以动态随机存储器(dynamic random access memory,DRAM)为代表的易失型存储设备在主存中的垄断地位,还有可能取代传统Flash和机械硬盘作为外存服务未来的计算机系统.如何综合各类新型存储的特性,设计高能效的存储架构,实现可应对大数据、云计算所需求的新型主存系统已经成为工业界和学术界的研究热点.提出基于高性能SOC FPGA阵列的NVM验证架构,互联多级FPGA,利用多层次FPGA结构扩展链接多片NVM.依据所提出的验证架构,设计了基于多层次FPGA的主从式NVM控制器,并完成适用于该架构的硬件原型设计.该架构不仅可以实现测试同类型多片NVM协同工作,也可以进行混合NVM存储管理方案验证.

A Survey of Non-Volatile Main Memory File Systems

Non-volatile memories(NVMs)provide lower latency and higher bandwidth than block devices.Besides,NVMs are byte-addressable and provide persistence that can be used as memory-level storage devices(non-volatile main memory,NVMM).These features change storage hierarchy and allow CPU to access persistent data using load/store instructions.Thus,we can directly build a file system on NVMM.However,traditional file systems are designed based on slow block devices.They use a deep and complex software stack to optimize file system performance.This design results in software overhead being the dominant factor affecting NVMM file systems.Besides,scalability,crash consistency,data protection,and cross-media storage should be reconsidered in NVMM file systems.We survey existing work on optimizing NVMM file systems.First,we analyze the problems when directly using traditional file systems on NVMM,including heavy software overhead,limited scalability,inappropriate consistency guarantee techniques,etc.Second,we summarize the technique of 30 typical NVMM file systems and analyze their advantages and disadvantages.Finally,we provide a few suggestions for designing a high-performance NVMM file system based on real hardware Optane DC persistent memory module.Specifically,we suggest applying various techniques to reduce software overheads,improving the scalability of virtual file system(VFS),adopting highly-concurrent data structures(e.g.,lock and index),using memory protection keys(MPK)for data protection,and carefully designing data placement/migration for cross-media file system.

面向NVM存储系统的快速文件访问系统

NVM存储设备系统具备提供高吞吐的潜质,包括接近内存的读写速度、字节寻址特性和支持多路转发等优势。但现有的系统软件栈并没有针对NVM去设计,使得系统软件栈存在许多影响系统访问性能的因素。通过分析发现文件系统的锁机制具有较大的开销,这使得数据的并发访问在多核心环境下成为一个难题。为了缓解这些问题,设计了无锁的文件读写机制以及基于字节的读写接口。通过取消基于文件的锁机制改变了粗粒度的访问控制,利用自主管理请求提高了进程的并发度;在设计能够利用字节寻址的新的文件访问接口时,不仅考虑了NVM存储设备的读写非对称,还考虑了其读写操作的不同特性。这些设计减少了软件栈的开销,有利于发挥NVM特性来提供一个高并发、高吞吐和耐久的存储系统。最后利用开源NVM模拟器PMEM实现了FPMRW原型系统,使用Filebench通用测试工具对FPMRW进行测试与分析,结果显示,FPMRW相对EXT+PMEM和XFS+PMEM能提高3%~40%的系统吞吐率。