Surface-type nonvolatile electric memory elements based on organic-on-organic CuPc-H_2Pc heterojunction

A novel surface-type nonvolatile electric memory elements based on organic semiconductors CuPc and H2Pc are fabricated by vacuum deposition of the CuPc and H2Pc films on preliminary deposited metallic （Ag and Cu） electrodes. The gap between Ag and Cu electrodes is 3040μm. For the current-voltage （I-V） characteristics the memory effect, switching effect, and negative differential resistance regions are observed. The switching mechanism is attributed to the electric-field-induced charge transfer. As a result the device switches from a low to a high-conductivity state and then back to a low conductivity state if the opposite polarity voltage is applied. The ratio of resistance at the high resistance state to that at the low resistance state is equal to 120-150. Under the switching condition, the electric current increases -- 80-100 times. A comparison between the forward and reverse I-V characteristics shows the presence of rectifying behavior.

Low voltage program-erasable Pd-Al_2O_3-Si capacitors with Ru nanocrystals for nonvolatile memory application

Pd-Al2O3-Si capacitors with Ru nanocrystals are fabricated and electrically characterized for nonvolatile memory application. While keeping the entire insulator Al2O3 thickness fixed, the memory window has a strong dependence on the tunneling layer thickness under low operating voltages, whereas it has weak dependence under high operating voltages. As for the optimal configuration comprised of 6-nm tunneling layer and 22-nm blocking layer, the resulting memory window increases from 1.5 V to 5.3 V with bias pulse increasing from 10-5 s to 10-2 s under ±7 V. A ten-year memory window as large as 5.2 V is extrapolated at room temperature after ±8 V/1 ms programming/erasing pulses.

Preparation of size controllable copper nanocrystals for nonvolatile memory applications

A method of fabricating Cu nanocrystals embedded in SiO2 dielectric film for nonvolatile memory applications by magnetron sputtering is introduced in this paper. The average size and distribution density of Cu nanocrystal grains are controlled by adjusting experimental parameters. The relationship between nanocrystal floating gate micro-structure and its charge storage capability is also discussed theoretically.

Improved performance of Au nanocrystal nonvolatile memory by N2-plasma treatment on HfO2blocking layer

The N2-plasma treatment on a HfO2 blocking layer of Au nanocrystal nonvolatile memory without any post annealing is investigated. The electrical characteristics of the MOS capacitor with structure of Al–Ta N/HfO2/Si O2/p-Si are also characterized. After N2-plasma treatment, the nitrogen atoms are incorporated into HfO2 film and may passivate the oxygen vacancy states. The surface roughness of HfO2 film can also be reduced. Those improvements of HfO2 film lead to a smaller hysteresis and lower leakage current density of the MOS capacitor. The N2-plasma is introduced into Au nanocrystal（NC） nonvolatile memory to treat the HfO2 blocking layer. For the N2-plasma treated device, it shows a better retention characteristic and is twice as large in the memory window than that for the no N2-plasma treated device. It can be concluded that the N2-plasma treatment method can be applied to future nonvolatile memory applications.

High-performance amorphous In–Ga–Zn–O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO_(2) heterojunction charge trapping stack

Amorphous In–Ga–Zn–O(a-IGZO)thin-film transistor(TFT)memories with novel p-SnO/n-SnO_(2) heterojunction charge trapping stacks(CTSs)are investigated comparatively under a maximum fabrication temperature of 280℃.Compared to a single p-SnO or n-SnO_(2) charge trapping layer(CTL),the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention.Of the two CTSs,the tunneling layer/p-SnO/nSnO_(2)/blocking layer architecture demonstrates much higher program efficiency,more robust data retention,and comparably superior erase characteristics.The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at-8 V/1 ms,and the ten-year memory window is extrapolated to be 4.41 V.This is attributed to shallow traps in p-SnO and deep traps in n-SnO_(2),and the formation of a built-in electric field in the heterojunction.

Scaling dependence of memory windows and different carrier charging behaviors in Si nanocrystal nonvolatile memory devices

Based on the charge storage mode,it is important to investigate the scaling dependence of memory performance in silicon nanocrystal（Si-NC） nonvolatile memory（NVM） devices for its scaling down limit.In this work,we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor（CMOS） technology.It is found that the memory windows of eight kinds of test key cells are almost the same of about1.64 V @ ±7 V/1 ms,which are independent of the gate area,but mainly determined by the average size（12 nm） and areal density（1.8×10^（11）/cm^2） of Si-NCs.The program/erase（P/E） speed characteristics are almost independent of gate widths and lengths.However,the erase speed is faster than the program speed of test key cells,which is due to the different charging behaviors between electrons and holes during the operation processes.Furthermore,the data retention characteristic is also independent of the gate area.Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.

Improved Operation Characteristics for Nonvolatile Charge-Trapping Memory Capacitors with High-κ Dielectrics and SiGe Epitaxial Substrates

A novel high-κ~ A1203/HfO2/AI203 nanolaminate charge trapping memory capacitor structure based on SiGe substrates with low interface densities is successfully fabricated and investigated. The memory capacitor exhibits excellent program-erasable characteristics. A large memory window of ~4 V, a small leakage current density of ~2 ×10-6 Acre-2 at a gate voltage of 7V, a high charge trapping density of 1.42 × 1013 cm-2 at a working vo]tage of 4-10 V and good retention characteristics are observed. Furthermore, the programming （△ VFB = 2.8 V at 10 V for 10μs） and erasing speeds （△VFB =-1.7 V at -10 V for 10μs） of the fabricated capacitor based on SiGe substrates are significantly improved as compared with counterparts reported earlier. It is concluded that the high-κ Al2O3/HfO2/Al2O3 nanolaminate charge trapping capacitor structure based on SiGe substrates is a promising candidate for future nano-scaled nonvolatile flash memory applications.

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition.The battery life is the critical problem for wearable devices. The non-volatile memory(NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption,NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory(DRAM). In this paper, we assume to use hybrid random access memory(RAM)and NVM architecture for the smart bracelet system.This paper presents a data management algorithm named bracelet power-aware data management(BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.

Design and Analysis of Low Power Hybrid Memristor-CMOS Based Distinct Binary Logic Nonvolatile SRAM Cell

Memristor is a newly found fourth circuit element for the next generation emerging nonvolatile memory technology. In this paper, design of new type of nonvolatile static random access memory cell is proposed by using a combination of memristor and complemented metal oxide semiconductor. Biolek memristor model and CMOS 180 nm technology are used to form a single cell. By introducing distinct binary logic to avoid safety margin is left for each binary logic output and enables better read/write data integrity. The total power consumption reduces from 0.407 mw (milli-watt) to 0.127 mw which is less than existing memristor based memory cell of the same CMOS technology. Read and write time is also significantly reduced. However, write time is higher than conventional 6T SRAM cell and can be reduced by increasing motion of electron in the memristor. The change of the memristor state is shown by applying piecewise linear input voltage.

支持高并发访问的新型NVM存储系统

I/O系统软件栈是影响NVM存储系统性能的重要因素。针对NVM存储系统的读写速度不均衡、写寿命有限等问题,设计了同异步融合的访问请求管理策略;在使用异步策略管理数据量较大的写操作的同时,仍然使用同步策略管理读请求和少量数据的写请求。针对多核处理器环境下不同计算核心访问存储系统时地址转换开销大的问题,设计了面向多核处理器地址转换缓存策略,减少地址转换的时间开销。最后实现了支持高并发访问NVM存储系统(CNVMS)的原型,并使用通用测试工具进行了随机读写、顺序读写、混合读写和实际应用负载的测试。实验结果表明,与PMBD相比,所提策略能提高1%～22%的读写速度和9%～15%的IOPS,验证了CNVMS策略能有效提高NVM存储系统的I/O性能和访问请求处理速度。

嵌入式Flash Memory Cell技术

本文分析了目前常用的快闪存储器(Flash Memory)存储单元结构,介绍了一种适用于嵌入的单元结构,存储器阵列设计、可靠性设计技术。

基于循环神经网络的多模态数据层次化缓存系统设计

为提升对多模态数据的管理效果,提高数据访问速度并减轻数据库负载,设计一种基于循环神经网络的多模态数据层次化缓存系统。在DRAM/NVM混合内存模块中,利用DRAM完成主存NVM的缓存。当DRAM存在缓存缺失时,利用访问监控模块内置高速采集卡来采集NVM上频繁访问4 KB数据块的历史访问记录,再将历史访问记录编码为访问向量后构建训练集,作为长短期记忆(LSTM)网络的输入,用于预测访问频率。在缓存过滤模块中,将访问频率预测结果高于设定阈值部分的4 KB多模态数据读取到DRAM中进行缓存。实验结果显示:所设计系统可最大程度地降低系统带宽占用情况,TLB缺失率低,缓存执行效率较高,面对大页面具备显著缓存优势。

一种支持大页的层次化DRAM/NVM混合内存系统

随着大数据应用的涌现,计算机系统需要更大容量的内存以满足大数据处理的高时效性需求.新型非易失性存储器(non-volatile memory,NVM)结合传统动态随机存储器(dynamic random access memory,DRAM)组成的混合内存系统具有内存容量大、功耗低的优势,因而得到了广泛关注.大数据应用同时也面临着旁路转换缓冲器(translation lookaside buffer,TLB)缺失率过高的性能瓶颈.大页可以有效降低TLB缺失率,然而,在混合内存中支持大页面临着大页迁移开销过大的问题.因此,设计了一种支持大页和大容量缓存的层次化混合内存系统:DRAM和NVM分别使用4KB和2MB粒度的页面分别进行管理,同时在DRAM和NVM之间实现直接映射.设计了基于访存频率的DRAM缓存数据过滤机制,减轻了带宽压力.提出了基于内存实时信息的动态热度阈值调整策略,灵活适应应用访存特征的变化.实验显示:与使用大页的全NVM内存系统和缓存热页(caching hot page,CHOP)系统相比平均有69.9%和15.2%的性能提升,而与使用大页的全DRAM内存系统相比平均只有8.8%的性能差距.

基于高性能SOC FPGA阵列的NVM验证架构设计与验证

新型非易失性存储器(non-volatile memory,NVM)技术日渐成熟,延迟越来越低,带宽越来越高,未来将不仅有可能取代以动态随机存储器(dynamic random access memory,DRAM)为代表的易失型存储设备在主存中的垄断地位,还有可能取代传统Flash和机械硬盘作为外存服务未来的计算机系统.如何综合各类新型存储的特性,设计高能效的存储架构,实现可应对大数据、云计算所需求的新型主存系统已经成为工业界和学术界的研究热点.提出基于高性能SOC FPGA阵列的NVM验证架构,互联多级FPGA,利用多层次FPGA结构扩展链接多片NVM.依据所提出的验证架构,设计了基于多层次FPGA的主从式NVM控制器,并完成适用于该架构的硬件原型设计.该架构不仅可以实现测试同类型多片NVM协同工作,也可以进行混合NVM存储管理方案验证.

面向NVM存储系统的快速文件访问系统

NVM存储设备系统具备提供高吞吐的潜质,包括接近内存的读写速度、字节寻址特性和支持多路转发等优势。但现有的系统软件栈并没有针对NVM去设计,使得系统软件栈存在许多影响系统访问性能的因素。通过分析发现文件系统的锁机制具有较大的开销,这使得数据的并发访问在多核心环境下成为一个难题。为了缓解这些问题,设计了无锁的文件读写机制以及基于字节的读写接口。通过取消基于文件的锁机制改变了粗粒度的访问控制,利用自主管理请求提高了进程的并发度;在设计能够利用字节寻址的新的文件访问接口时,不仅考虑了NVM存储设备的读写非对称,还考虑了其读写操作的不同特性。这些设计减少了软件栈的开销,有利于发挥NVM特性来提供一个高并发、高吞吐和耐久的存储系统。最后利用开源NVM模拟器PMEM实现了FPMRW原型系统,使用Filebench通用测试工具对FPMRW进行测试与分析,结果显示,FPMRW相对EXT+PMEM和XFS+PMEM能提高3%~40%的系统吞吐率。

Improvement of Electrical Properties of the Ge2Sb2Te5 Film by Doping Si for Phase-Change Random Access Memory

Si-doped Ge2Sb2Te5 films have been prepared by dc magnetron co-sputtering with Ge2Sb2Te5 and Si targets. The addition of Si in the Ge2Sb2Te5 film results in the increase of both crystallization temperature and phasetransition temperature from face-centred-cubic （fcc） phase to hexagonal （hex） phase. The resistivity of the Ge2Sb2Te5 film shows a significant increase with the Si doping. When doping 11.8 at.% of Si in the film, the resistivity after 460℃ annealing increases from 1 to 11 mΩ.cm and dynamic resistance increase from 64 to 99Ω compared to the undoped Ge2Sb2Te5 film. This is very helpful to writing current reduction of phase-change random access memory.

Total Dose Radiation Tolerance of Phase Change Memory Cell with GeSbTe Alloy

Phase change memory （PCM） cell array is fabricated by a standard complementary metal-oxide-semiconductor process and the subsequent special fabrication technique. A chalcogenide Ge2Sb2Te5 film in thickness 50hm deposited by rf magnetron sputtering is used as storage medium for the PCM cell. Large snap-back effect is observed in current-voltage characteristics, indicating the phase transition from an amorphous state （higher resistance state） to the crystalline state （lower resistance state）. The resistance of amorphous state is two orders of magnitude larger than that of the crystalline state from the resistance measurement, and the threshold current needed for phase transition of our fabricated PCM cell array is very low （only several μA）. An x-ray total dose radiation test is carried out on the PCM cell array and the results show that this kind of PCM cell has excellent total dose radiation tolerance with total dose up to 2 ×10^6 rad（Si）, which makes it attractive for space-based applications.

BOOM-KV:基于RDMA的高性能NVM键值数据库

随着英特尔傲腾数据中心持久化内存模块(DCPMM)开始进入市场以及远程直接内存访问(RDMA)硬件成本的降低,设计融合非易失性内存(NVM)和RDMA的键值(KV)数据库面临新的机遇和挑战。构建基于NVM和RDMA的KV数据库的关键在于设计一个高效的通信协议。遗憾的是,现有工作或采用NVM不感知的RDMA协议,或采用低效的NVM感知的RDMA协议,这导致它们无法最大化KV数据库的性能。本文提出了BOOM协议——一种新型的NVM感知的RDMA协议。相较于NVM不感知的协议,BOOM协议允许直接对远端NVM进行RDMA操作,消除了冗余的数据拷贝;相较于现有的NVM感知的协议,它可以显著减少元数据请求,降低KV请求的端对端延迟。在BOOM协议的基础上构建了BOOM-KV,并针对服务端中央处理器(CPU)利用率和宕机持久化等问题进一步进行优化。将BOOM-KV与最新的研究成果进行对比,结果表明,BOOM-KV能显著降低请求延迟,其中PUT延迟最大降低了42%,GET延迟最大降低了41%,并且展现出良好的扩展性。

非易失性内存友好的线性哈希索引——NVM-LH

非易失性内存(NVM)因其大容量、持久化、按位存取和读延迟低等特性而受到人们的关注,但它同时也具有写次数有限、读写速度不均衡等缺点。针对传统线性哈希索引直接在NVM上实现时会导致大量的随机写操作这一问题,提出了一种新的NVM友好的线性哈希索引NVM-LH。NVM-LH通过存储数据时的缓存行对齐实现了缓存友好性,同时提出了无日志的数据一致性保证策略。此外,NVM-LH还通过优化分裂和删除操作来减少NVM写操作。实验结果表明,NVM-LH在空间利用率上比CCEH高30%,在NVM写次数上比CCEH减少了15%左右,表现了更好的NVM友好性。

Improvement of memory characteristics by employing a charge trapping layer with combining bent and flat energy bands

Designed ZrxSi1-xO2 films with combining bent and flat energy bands are employed as a charge trapping layer for memory capacitors.Compared to a single bent energy band,the bandgap structure with combining bent and flat energy bands exhibits larger memory window,faster program/erase speed,lower charge loss even at 200℃ for 104s,and wider temperature insensitive regions.The tunneling thickness together with electron recaptured efficiency in the trapping layer,and the balance of two competing electron loss mechanisms in the bent and flat energy band regions collectively contribute to the improved memory characteristics.Therefore,the proposed ZrxSi1-xO2 with combining bent and flat energy bands should be a promising candidate for future nonvolatile memory applications,taking into consideration of the trade-off between the operation speed and retention characteristics.