Patterned Dual pn Junctions Restraining Substrate Loss of an On-Chip Inductor

Dual pn junctions in lateral and vertical directions are formed by diffusing the p^＋ on the patterned n-well in standard CMOS technology, which are inserted under the inductor in order to reduce the currents in the substrate induced by the electromagnetic field from the inductor. The thickness of high resistance is not equivalent to the width of the depletion region of the vertical pn junctions,but the depth of the bottom pn junction in the substrate are both proposed and validated. For the first time, through the grounded p^＋-diffusion layer shielding the suhstrate from the electric field of the inductor, the width of the depletion regions of the lateral and vertical pn junctions are changed by increasing the voltage applied to the n wells. The quality factor is improved or reduced with the thickness of high resistance by 19%. This phenomenon validates the theory that the pn junction substrate isolation can reduce the loss caused by the currents in the substrate induced by the electromagnetic field from the inductor.

On-Chip Inductor Technique for Improving LNA Performance Operating at 15 GHz

This paper presents a technique for low noise figure reduction of low-noise amplifier (LNA). The proposed LNA is designed in a source degeneration technique that offers lower noise figure. The resistance of the on-chip inductor is reduced by using multilayer that significantly reduces the thermal noise due to spiral inductor. Also, using spiral inductor as a gate inductor reduces the effect of the input parasitic capacitance on the noise figure and provides a good matching at the input and output of the LNA. The results of the LNA using multilayer on-chip inductor compared will off-chip inductor have been illustrated. It shows that the proposed technique reduces significantly the noise figure and improves the matching. The proposed LNA is designed in 0.13 μm process with 1.3 V supply voltage and simulated using Advanced Design System (ADS) software. The simulation results show that the LNA is unconditionally stable and provides a forward gain of 11.087 dB at operating frequency of 15 GHz with 1.784 dB noise figure and input and output impedance matching of –17.93 dB, and –10.04 dB.

A New Method for Optimizing Layout Parameter ofan Integrated On-Chip Inductor in CMOSRF IC's

Analyzing the influence on Q factor, which was caused by the parasitic effect in a CMOS RF on chip integrated inductor, a concise method to increase the Q factor has been obtained when optimizing the layout parameter. Using this method, the Q factor of 7.9 can be achieved in a 5nH inductor (operating frequency is 2GHz) while the errors in inductance are less than 0.5% compared with the aimed values. It is proved by experiments that this method can guarantee the sufficient accuracy but require less computation time. Therefore, it is of great use for the design of the inductor in CMOS RF IC’s.

On-Chip Micro Temperature Controllers Based on Freestanding Thermoelectric Nano Films for Low-Power Electronics

Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.

High-intensity spatial-mode steerable frequency up-converter toward on-chip integration

Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domains without disturbing their quantum properties,nonlinear frequency conversion,typically steered with the quadratic(χ2)process,should be considered.Furthermore,another degree of freedom in steering the spatial modes during theχ2 process,with unprecedent mode intensity is proposed here by modulating the lithium niobate(LN)waveguide-based inter-mode quasi-phasematching conditions with both temperature and wavelength parameters.Under high incident light intensities(25 and 27.8 dBm for the pump and the signal lights,respectively),mode conversion at the sum-frequency wavelength with sufficient high output power(−7–8 dBm)among the TM01,TM10,and TM00 modes is realized automatically with characterized broad temperature(ΔT≥8°C)and wavelength windows(Δλ≥1 nm),avoiding the previous efforts in carefully preparing the signal or pump modes.The results prove that high-intensity spatial modes can be prepared at arbitrary transparent wavelength of theχ2 media toward on-chip integration,which facilitates the development of chip-based communication and quantum information systems because spatial correlations can be applied to generate hyperentangled states and provide additional robustness in quantum error correction with the extended Hilbert space.

A Novel Lateral Solenoidal On-Chip Integrated Inductor Implemented in Conventional Si Process

A new structure of the on- chip integrated inductors im plem ented in conventional Si process is presented as a lateral solenoid.The fabrication process utilizes a conventional Si technology with standard double- layer m etal- lization.S param eters of the inductors based equivalent circuit are investigated and the inductor parameters are cal- culated from the m easured data.Experimental results are presented on an integrated inductors fabricated in a lateral solenoid type utilizing double m etal layers rather than a single metal layer as used in conventional planar spiral de- vices.Inductors with peak Q of 1.3and inductance value of 2 .2 n H are presented,which are com parable to conven- tional planar spiral inductors.

An improved single-π equivalent circuit model for on-chip inductors in GaAs process

An improved single-π equivalent circuit model for on-chip inductors in the GaAs process is presented in this paper. Considering high order parasites, the model is established by comprising an improved skin effect branch and a substrate lateral coupling branch. The parameter extraction is based on an improved characteristic function approach and vector fitting method. The model has better simulation than the previous work over the measured data of 2.5r and 4.5r on-chip inductors in the GaAs process.

一种基于耦合电感的高增益软开关谐振变换器

该文提出了一种具有高增益、软开关的新型谐振变换器。该谐振变换器使用耦合电感来提高电压增益,升压比不仅取决于占空比,还取决于耦合电感的变比,具有高增益的优点。此外,由于采用了有源钳位技术,漏感中的能量可以被回收利用,用来对开关管的结电容充放电提供能量,从而实现软开关。由于采用了耦合电感,所提出的变换器可以在较低的开关管电压应力的情况下实现较高的输出电压,因此可以使用低导通电阻的低压器件,从而提升系统的效率。该文分析了该谐振变换器的工作原理,并推导了输出电压、关断电流应力等参数的解析表达式。在此基础上,从理论上分析了该变换器取得软开关的条件,并对该变换器的各个器件的电压电流应力进行分析,为器件选型提供了理论依据。最后,搭建1kW实验样机,针对该文提出的基于耦合电感的谐振变换器的高增益、软开关、低电压应力、高效率等性能进行了实验验证。通过实验得出所提出的拓扑可以在10倍增益的情况下达到最高97.5%的效率,表明所提拓扑的优越性。

一种应用于两相交错Boost的耦合电感的优化设计

两相交错Boost变换器具有纹波电流小的优势,但其采用的交错并联技术增加了电感数量,进而增加了装置的体积和重量,不利于其功率密度的提升。耦合电感通过将多个磁性元件集成到一个磁芯实现磁路的部分共享,从而减小了磁元件的数量和重量。因此,设计了一种反向耦合电感,并将其应用于两相交错Boost变换器,实现了装置功率密度的提升。首先,对反向耦合电感的工作原理和损耗来源进行分析;然后,在此基础上设计了一种改进的“EE”型磁芯,一方面有效提高了磁芯利用率,另一方面降低了电感的体积与重量;最后,通过有限元仿真对所提优化设计方案进行验证,同时搭建了功率等级为2 kW的两相交错Boost变换器实验平台。仿真和实验结果均验证了所提优化设计方案的有效性。

基于开关电感的宽电压增益双向DC/DC变换器

此处提出了一种用于储能系统的基于开关电感的宽电压增益双向DC/DC变换器。该变换器在实现双向升降压的同时进一步扩大了双向变换器的电压增益,可以适应不同电压等级的储能电池;相同电压增益下功率器件占空比有效降低,进一步减小了输入电流纹波,有助于提高电池充电性能。分析了放电和充电两种工作模式的工作原理,并搭建实验样机进行验证。实验结果表明在输出电压稳定的工况下,该变换器放电模式可以实现0.5~5倍的电压增益,充电模式可以实现0.2~2倍的电压增益,证明了所提变换器的双向升降压能力和宽电压增益能力。

基于二次型升压变换器和开关电容的混合式升压方案研究

提出一种混合式高升压比DC-DC变换器。该变换器由二次型升压变换器、开关电容和耦合电感单元集成。为了减少元件的数量,耦合电感一次侧与二次型升压变换器共用;二次型升压变换器的输出电容一分为二,并与开关电容共用。由于电源和负载之间的共地特性,则输入电流连续。对所提变换器的电压增益进行了推导,并分析其电压应力。结果表明所提逆变器具备高电压增益、低电压应力的特性。最后,搭建了80 W的实验样机,实验结果验证了所提变换器的正确性和有效性。

一种应用于光伏的高增益DC/DC变换器研究

基于耦合电感、开关电容与输入电压源组成的基本功率单元,提出一种集成式新型DC/DC变换器。该拓扑结构具有模块化和可扩展性,耦合电感和开关电容结构组成的倍压单元提升了电路的升压比。漏感能量通过钳位电路回收,以降低开关管电压应力和功率损耗;同时缓解了二极管的反向恢复问题,优化了开关管和二极管的选择。详细介绍了稳态分析、工作原理和设计考虑;最后并制作了90 W实验样机,验证了理论分析的正确性。

基于寄生电感优化的分立器件布局方法研究

为了探究分立器件与PCB组合形成的半桥电路时采用何种布局方式才能尽最大限度减小线路寄生电感的问题,基于换流回路寄生电感概念,提出了一种经优化的分立器件在PCB上的布局方式,进而减小换流回路的寄生电感,随后通过有限元仿真软件评估并验证不同布局方式所产生的寄生电感,并结合LTspice电路仿真软件评估不同布局方式对器件电开关特性的影响,最后通过双脉冲实验验证了所设计的一种经过优化布局半桥电路的优越性.所提供的半桥电路的设计方法为分立器件在PCB上的布局提供了理论和技术支撑.

一种交叉倍压型高增益DC/DC变换器

针对光伏发电、燃料电池发电等领域对高增益直流变换器的需求,以两相交错并联升压变换器为研究对象,由2个含有电感的倍压单元组合设计出实现电压提升的交叉倍压结构,据此提出了一种新颖的交叉倍压型高增益DC/DC变换器。该变换器可实现(3n+4)/(1-d)倍的高电压增益(1∶n为耦合电感匝数比,d为变换器占空比),且具有电路器件的低电压应力特性。对于漏感引起的开关管电压尖峰问题,引入了钳位电容构成释放漏感能量通道,同时提升了输出电压。介绍了新型交叉倍压型高增益变换器的拓扑结构,分析了变换器各模态的工作过程,推导了电压增益、输入电流纹波及各器件电压应力等稳态特性,并搭建样机进行实验研究,验证了该直流变换技术方案的可行性和先进性。

高增益耦合电感组合Boost-Cuk变换器

为了解决传统变换器电压增益低的问题,将Boost变换器与Cuk变换器进行并联集成,并利用耦合电感倍压技术提高变换器的电压增益。设计而成的高增益耦合电感组合Boost-Cuk变换器保留了Cuk变换器输出电流的连续性,新型结构中使用无源钳位来吸收漏感能量,对寄生电容与漏感谐振引起的电压尖峰起到约束作用,降低了开关管的电压应力。描述了变换器电感电流连续模式(Continuous current mode,CCM)下的运行特点,并进行了该变换器的参数设计。最后,通过搭建一台100 W的试验样机来求证理论的正确性。

新型高增益耦合电感二次型变换器

将开关-耦合电感单元引入二次型变换器,采用一个耦合电感和两个独立电感,在开关管关断时,电感为电容充电;导通时,利用电容为负载供电。与传统变换器相比,所提出的变换器采用更少的器件,能得到高电压增益效果与低占空比。采用了降低电压应力的电容,二极管和半导体开关,开关管应力更低。提出了稳态和比较性能分析,制作了一台140W实验平台,给出实验数据与结论,验证了理论分析的正确性。

集成有源开关电感和Y源倍压单元的高增益DC-DC变换器

针对光伏发电系统中光伏组件电压等级的提升,提出一种集成有源开关电感和Y源倍压单元的高增益DC-DC变换器。所提变换器能够实现低开关管电压应力,具有高自由度电压调节能力,在满足一定升压条件下仍能保证电路的效率,在光伏发电中具有较大的应用潜力。对变换器的工作模态、器件电压电流应力、参数设计和损耗效率进行详细阐述。最后通过实验验证所提拓扑结构的可行性。

卧式反应釜电磁感应加热设计

针对大型反应釜的感应加热难以进行大量实验验证的问题,通过将理论计算与有限元仿真相结合的方式,对计算得出的参数进行优化,选择合适的输出功率和谐振频率,完成感应器的设计。通过仿真可以更好对比不同匝数、自热对流和搅拌轴对加热的影响,更直观地查看工件温度分布情况,缩小计算参数误差,实现反应釜加热的工艺要求。

考虑电感饱和的逆变器变开关频率控制仿真

不当操作会导致电感饱和状态下逆变器功率损耗严重,为了提升频率控制的稳定性,提出考虑电感饱和的逆变器变开关频率控制方法。根据逆变器的构成获取相关参数的矢量关系,利用基尔霍夫电压定律生成电感饱和状态的逆变器数学模型,通过旋转构建逆变器在dp坐标系下的数学模型,用于预测推导逆变器的电压值。设计开关控制的三大核心成分,分别为功率鉴定器、频率鉴定器和频率滞环比较器,利用电压定向矢量控制方法分别从三个核心成分中得出逆变器的损耗、功率控制结果以及频率状态量误差,完成逆变器变开关频率控制。实验结果表明,所提方法的电压控制效果较好,频率控制稳定性较高。

基于MPC的耦合电感飞跨电容双向DC/DC变换器功率均衡解耦控制策略

耦合电感功率变换器因耦合电感阻抗、电感值等参数差异易导致功率不均衡。针对耦合电感飞跨电容双向DC/DC变换器,提出一种基于模型预测控制(MPC)的功率均衡解耦控制策略。通过对变换器原理进行分析,建立基于电感电流解耦的数学模型,得到包括电感电流和飞跨电容电压等6个控制变量的解耦控制方法。在此基础上,提出基于MPC的功率均衡解耦控制策略。同时,为降低MPC算法的运算负荷,根据解耦控制模型重构模型预测价值函数,实现各控制变量独立动态寻优,使系统能在稳定控制输出电压及飞跨电容电压的同时,实现两相耦合电感的功率均衡控制。最后,通过理论分析及实验对所提策略进行有效验证。