Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can...Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.展开更多
Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity ...Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.展开更多
Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domai...Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domains without disturbing their quantum properties,nonlinear frequency conversion,typically steered with the quadratic(χ2)process,should be considered.Furthermore,another degree of freedom in steering the spatial modes during theχ2 process,with unprecedent mode intensity is proposed here by modulating the lithium niobate(LN)waveguide-based inter-mode quasi-phasematching conditions with both temperature and wavelength parameters.Under high incident light intensities(25 and 27.8 dBm for the pump and the signal lights,respectively),mode conversion at the sum-frequency wavelength with sufficient high output power(−7–8 dBm)among the TM01,TM10,and TM00 modes is realized automatically with characterized broad temperature(ΔT≥8°C)and wavelength windows(Δλ≥1 nm),avoiding the previous efforts in carefully preparing the signal or pump modes.The results prove that high-intensity spatial modes can be prepared at arbitrary transparent wavelength of theχ2 media toward on-chip integration,which facilitates the development of chip-based communication and quantum information systems because spatial correlations can be applied to generate hyperentangled states and provide additional robustness in quantum error correction with the extended Hilbert space.展开更多
Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip ...Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip （NoC）. Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture： multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.展开更多
As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3...As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3D integration has the higher packing density and the shorter wire length. Therefore,the 3D ONoC will have the great potential in the future. In this paper,we first discuss the existing ONoC researches,and then design mesh and torus ONoCs from the perspectives of topology,router,and routing module,with the help of 3D integration. A simulation platform is established by using OPNET to compare the performance of 2D and 3D ONoCs in terms of average delay and packet loss rate. The performance comparison between 3D mesh and 3D torus ONoCs is also conducted. The simulation results demonstrate that 3D integration has the advantage of reducing average delay and packet loss rate,and 3D torus ONoC has the better performance compared with 3D mesh solution. Finally,we summarize some future challenges with possible solutions,including microcosmic routing inside optical routers and highly-efficient traffic grooming.展开更多
We report a strict non-blocking four-port optical router that is used for a mesh photonic network-on-chip on a silicon-on-insulator platform.The router consists of eight silicon microring switches that are tuned by th...We report a strict non-blocking four-port optical router that is used for a mesh photonic network-on-chip on a silicon-on-insulator platform.The router consists of eight silicon microring switches that are tuned by the thermo-optic effect.For each tested rousting state,the signal-to-noise ratio of the optical router is larger than 13.8 dB at the working wavelength.The routing functionality of the device is verified.We perform 40 Gbps nonreturn to zero code data transmission on its 12 optical links.Meanwhile,data transmission using wavelength division multiplexing on eight channels in the C band(from 1525 to 1565 nm)has been adopted to increase the communication capacity.The optical router’s average energy efficiency is 25.52 fJ/bit.The rising times(10%to 90%)of the eight optical switch elements are less than 10μs and the falling times(90%-10%)are less than 20μs.展开更多
Based on a ripped-up and rerouted methodology,a multilayer area detailed router is presented by using simulated evolution technique.A modified maze algorithm is also performed for the single net.
On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In t...On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.展开更多
能量路由器是能源互联网领域的核心设备,其电路拓扑能够实现新能源、储能、各类负荷的统一分配。目前,能量路由器缺乏配电网故障恢复能力。该文提出一种实现故障调控与新能源消纳的多端口能量路由器(multi‐port energy router,MP‐ER)...能量路由器是能源互联网领域的核心设备,其电路拓扑能够实现新能源、储能、各类负荷的统一分配。目前,能量路由器缺乏配电网故障恢复能力。该文提出一种实现故障调控与新能源消纳的多端口能量路由器(multi‐port energy router,MP‐ER)。首先,介绍MP‐ER拓扑及原理,根据MP‐ER整体结构,提出以直流母线电压为主信号,各个端口分散控制的控制策略;其次,通过直流母线电压及配电网零序电压情况,将MP‐ER工作模式分为正常模式和故障柔性消弧两种模式,在所提的控制策略下,实现各模态内的稳定、高效运行;最后,针对连接的微网、配电网系统,利用MATLAB数值软件,对该模型进行仿真并验证该文提出的拓扑结构功能的合理性。该研究为能量路由器的研究提出一种新的拓扑结构和模型。展开更多
文摘Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.
基金The authors thank D.Berger,D.Hofmann and C.Kupka in IFW Dresden for helpful technical support.H.R.acknowledges funding from the DFG(Deutsche Forschungsgemeinschaft)within grant number RE3973/1-1.Q.J.,H.R.and K.N.conceived the work.With the support from N.Y.and X.J.,Q.J.and T.G.fabricated the thermoelectric films and conducted the structural and compositional characterizations.Q.J.prepared microchips and fabricated the on-chip micro temperature controllers.Q.J.and N.P.carried out the temperature-dependent material and device performance measurements.Q.J.and H.R.performed the simulation and analytical calculations.Q.J.,H.R.and K.N.wrote the manuscript with input from the other coauthors.All the authors discussed the results and commented on the manuscript.
文摘Multidimensional integration and multifunctional com-ponent assembly have been greatly explored in recent years to extend Moore’s Law of modern microelectronics.However,this inevitably exac-erbates the inhomogeneity of temperature distribution in microsystems,making precise temperature control for electronic components extremely challenging.Herein,we report an on-chip micro temperature controller including a pair of thermoelectric legs with a total area of 50×50μm^(2),which are fabricated from dense and flat freestanding Bi2Te3-based ther-moelectric nano films deposited on a newly developed nano graphene oxide membrane substrate.Its tunable equivalent thermal resistance is controlled by electrical currents to achieve energy-efficient temperature control for low-power electronics.A large cooling temperature difference of 44.5 K at 380 K is achieved with a power consumption of only 445μW,resulting in an ultrahigh temperature control capability over 100 K mW^(-1).Moreover,an ultra-fast cooling rate exceeding 2000 K s^(-1) and excellent reliability of up to 1 million cycles are observed.Our proposed on-chip temperature controller is expected to enable further miniaturization and multifunctional integration on a single chip for microelectronics.
基金financial supports from National Key Research and Development Program of China(2021YFB3602500)Self-deployment Project of Fujian Science&Technology Innovation Laboratory for Optoelectronic Information of China(2021ZZ101)National Natural Science Foundation of China(Grant Nos.62275247 and 61905246).
文摘Integrated photonic devices are essential for on-chip optical communication,optical-electronic systems,and quantum information sciences.To develop a high-fidelity interface between photonics in various frequency domains without disturbing their quantum properties,nonlinear frequency conversion,typically steered with the quadratic(χ2)process,should be considered.Furthermore,another degree of freedom in steering the spatial modes during theχ2 process,with unprecedent mode intensity is proposed here by modulating the lithium niobate(LN)waveguide-based inter-mode quasi-phasematching conditions with both temperature and wavelength parameters.Under high incident light intensities(25 and 27.8 dBm for the pump and the signal lights,respectively),mode conversion at the sum-frequency wavelength with sufficient high output power(−7–8 dBm)among the TM01,TM10,and TM00 modes is realized automatically with characterized broad temperature(ΔT≥8°C)and wavelength windows(Δλ≥1 nm),avoiding the previous efforts in carefully preparing the signal or pump modes.The results prove that high-intensity spatial modes can be prepared at arbitrary transparent wavelength of theχ2 media toward on-chip integration,which facilitates the development of chip-based communication and quantum information systems because spatial correlations can be applied to generate hyperentangled states and provide additional robustness in quantum error correction with the extended Hilbert space.
基金This work was supported by the National High Technology Research and Development 863 Program of China under Grant No. 2015AA01A301, the National Natural Science Foundation of China under Grant No. 61332009, the National HeGaoJi Project of China under Grant No. 2013ZX0102-8001-001-001, and the Beijing Municipal Science and Technology Commission under Grant Nos. Z15010101009 and Z151100003615006.
文摘Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip （NoC）. Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture： multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.
基金supported in part by the National Nat-ural Science Foundation of China(Grant Nos.61401082,61471109,61502075,61672123,91438110,U1301253)the Fundamental Research Funds for Central Universities(Grant Nos.N161604004,N161608001,N150401002,DUT15RC(3)009)Liaoning Bai Qian Wan Talents Program,and National High-Level Personnel Special Support Program for Youth Top-Notch Talent
文摘As a nanometer-level interconnection,the Optical Network-on-Chip(ONoC)was proposed since it was typically characterized by low latency,high bandwidth and power efficiency. Compared with a 2-Dimensional(2D)design,the 3D integration has the higher packing density and the shorter wire length. Therefore,the 3D ONoC will have the great potential in the future. In this paper,we first discuss the existing ONoC researches,and then design mesh and torus ONoCs from the perspectives of topology,router,and routing module,with the help of 3D integration. A simulation platform is established by using OPNET to compare the performance of 2D and 3D ONoCs in terms of average delay and packet loss rate. The performance comparison between 3D mesh and 3D torus ONoCs is also conducted. The simulation results demonstrate that 3D integration has the advantage of reducing average delay and packet loss rate,and 3D torus ONoC has the better performance compared with 3D mesh solution. Finally,we summarize some future challenges with possible solutions,including microcosmic routing inside optical routers and highly-efficient traffic grooming.
基金National Key Research and Development Program of China(2019YFB2203602)National Science Fund for Distinguished Young Scholars(61825504).
文摘We report a strict non-blocking four-port optical router that is used for a mesh photonic network-on-chip on a silicon-on-insulator platform.The router consists of eight silicon microring switches that are tuned by the thermo-optic effect.For each tested rousting state,the signal-to-noise ratio of the optical router is larger than 13.8 dB at the working wavelength.The routing functionality of the device is verified.We perform 40 Gbps nonreturn to zero code data transmission on its 12 optical links.Meanwhile,data transmission using wavelength division multiplexing on eight channels in the C band(from 1525 to 1565 nm)has been adopted to increase the communication capacity.The optical router’s average energy efficiency is 25.52 fJ/bit.The rising times(10%to 90%)of the eight optical switch elements are less than 10μs and the falling times(90%-10%)are less than 20μs.
文摘Based on a ripped-up and rerouted methodology,a multilayer area detailed router is presented by using simulated evolution technique.A modified maze algorithm is also performed for the single net.
文摘On-chip global buses in deep sub-micron designs consume significant amounts of energy and have large propagation delays. Thus, minimizing energy dissipation and propagation delay is an important design objective. In this paper, we propose a new spatial and temporal encoding approach for generic on-chip global buses with repeaters that enables higher performance while reducing peak energy and average energy. The proposed encoding approach exploits the benefits of a temporal encoding circuit and spatial bus-invert coding techniques to simultaneously eliminate opposite transitions on adjacent wires and reduce the number of self-transitions and coupling-transitions. In the design process of applying encoding techniques for reduced bus delay and energy, we present a repeater insertion design methodology to determine the repeater size and inter-repeater bus length, which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. This methodology is employed to obtain optimal energy versus delay trade-offs under slew-rate constraints for various encoding techniques.
文摘能量路由器是能源互联网领域的核心设备,其电路拓扑能够实现新能源、储能、各类负荷的统一分配。目前,能量路由器缺乏配电网故障恢复能力。该文提出一种实现故障调控与新能源消纳的多端口能量路由器(multi‐port energy router,MP‐ER)。首先,介绍MP‐ER拓扑及原理,根据MP‐ER整体结构,提出以直流母线电压为主信号,各个端口分散控制的控制策略;其次,通过直流母线电压及配电网零序电压情况,将MP‐ER工作模式分为正常模式和故障柔性消弧两种模式,在所提的控制策略下,实现各模态内的稳定、高效运行;最后,针对连接的微网、配电网系统,利用MATLAB数值软件,对该模型进行仿真并验证该文提出的拓扑结构功能的合理性。该研究为能量路由器的研究提出一种新的拓扑结构和模型。
