A low power 12-bit 30 MSPS CMOS pipeline ADC with on-chip voltage reference buffer

A 12-bit 30 MSPS pipeline analog-to-digital converter （ADC） implemented in 0.13μm 1P8M CMOS technology is presented. Low power design with the front-end sample-and-hold amplifier removed is proposed. Except for the first stage, two-stage cascode-compensated operational amplifiers with dual inputs are shared between successive stages to further reduce power consumption. The ADC presents 65.3 dB SNR, 75.8 dB SFDR and 64.6 dBSNDR at 5 MHz analog input with 30.7 MHz sampling rate. The chip dissipates 33.6 mW from 1.2 V power supply. FOM is 0.79 pJ/conv step.

High-PSRR High-Order Curvature-Compensated CMOS Bandgap Voltage Reference

A high-PSRR high-order curvature-compensated CMOS bandgap voltage reference( BGR),which has the performances of high power supply rejection ratio( PSRR) and low temperature coefficient,is designed in SMIC 0. 18 μm CMOS process. Compared to the conventional curvature-compensated BGR which adopted a piecewise-linear current,the temperature characterize of the proposed BGR is effectively improved by adopting two kinds of current including a piecewise-linear current and a current proportional 1. 5 party to the absolute temperature T. By adopting a low dropout( LDO) regulator whose output voltage is the operating supply voltage of the proposed BGR core circuit instead of power supply voltage VDD,the proposed BGR with LDO regulator achieves a well PSRR performance than the BGR without LDO regulator. Simulation results show that the proposed BGR with LDO regulator achieves a temperature coefficient of 2. 1 × 10-6/ ℃ with a 1. 8 V power supply voltage and a line regulation of 4. 9 μV / V at 27 ℃. The proposed BGR with LDO regulator at 10 Hz,100 Hz,1 k Hz,10 k Hz and 100 k Hz have the PSRR of- 106. 388,- 106. 388,- 106. 38,- 105. 93 and-88. 67 d B respectively.

New Curvature-Compensated CMOS Bandgap Voltage Reference

A novel curvature-compensated CMOS bandgap voltage reference is presented. The reference utilizes two first order temperature compensations generated from the nonlinearity of the finite current gain β of vertical pnp bipolar transistor. The proposed circuit, designed in a standard 0.18 μm CMOS process, achieves a good temperature coefficient of 2.44 ppm/℃ with temperature range from --40℃ to 85 ℃, and about 4 mV supply voltage variation in the range from 1.4 V to 2.4 V. With a 1.8 V supply voltage, the power supply rejection ratio is -56dB at 10MHz.

A band-gap voltage reference for interface circuit of microsensor

A high performance CMOS band-gap voltage reference circuit that can be used in interface integrated circuit of microsensor and compatible with 0. 6 μm ( double poly) mix process is proposed in this paper. The circuit can be employed in the range of 1. 8 - 8 V and carry out the first-order PTAT ( proportional to absolute temperature) temperature compensation. Through using a two-stage op-amp with a NMOS input pair as a negative feedback op-amp,the PSRR ( power supply rejection ratio) of the entire circuit is increased,and the temperature coefficient of reference voltage is decreased. Results from HSPICE simulation show that the PSRR is - 72. 76 dB in the condition of low-frequency,the temperature coefficient is 2. 4 × 10 -6 in the temperature range from - 10 ℃ to 90 ℃ and the power dissipation is only 14 μW when the supply voltage is 1. 8 V.

Curvature Compensated CMOS Bandgap Reference with Novel Process Variation Calibration Technique

A lowtemperature coefficient（ TC） bandgap reference（ BGR） with novel process variation calibration technique is proposed in this paper. This proposed calibration technique compensating both TC and output value of BGR achieves fine adjustment step towards the reference voltage,while keeping optimal TC by utilizing large resistance to help layout match. The high-order curvature compensation realized by poly and p-diffusion resistors is introduced into the design to guarantee the temperature characteristic. Implemented in 180 nm technology,the proposed BGR has been simulated to have a power supply rejection ratio（ PSRR） of 91 dB@100 Hz. The calibration technique covers output voltage scope of 0. 49 V-0. 56 Vwith TC of 9. 45 × 10^（-6）/℃-9. 56 × 10^（-6）/℃ over the temperature range of-40 ℃-120 ℃. The designed BGR provides a reference voltage of 500 mV,with measured TC of 10. 1 × 10^（-6）/℃.

Novel High PSRR Current Reference Based on Subthreshold MOSFETs

This paper takes full advantages of the I-V transconductance characteristics of metal-oxide semiconductor field effect transistor （MOSFET） operating in the subthreshold region and the enhancement pre-regulator technique with the high gain negative feedback loop. The proposed reference circuit, designed with the SMIC 0.18 μm standard complementary metal-oxide semiconductor （CMOS） logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient （TC） of 2.5×10^-4μA/℃ in the temperature range of-40 to 150℃ at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about - 126 dB at DC frequency and remains -92 dB at the frequency higher 100 MHz. Moreover the proposed reference circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.

Adaptive Reference Power Based Voltage Droop Control for VSC-MTDC Systems

Featuring low communication requirements and high reliability,the voltage droop control method is widely adopted in the voltage source converter based multi-terminal direct current(VSC-MTDC)system for autonomous DC voltage regulation and power-sharing.However,the traditional voltage droop control method with fixed droop gain is criticized for over-limit DC voltage deviation in case of large power disturbances,which can threaten stable operation of the entire VSCMTDC system.To tackle this problem,this paper proposes an adaptive reference power based voltage droop control method,which changes the reference power to compensate the power deviation for droop-controlled voltage source converters(VSCs).Besides retaining the merits of the traditional voltage droop control method,both DC voltage deviation reduction and power distribution improvement can be achieved by utilizing local information and a specific control factor in the proposed method.Basic principles and key features of the proposed method are described.Detailed analyses on the effects of the control factor on DC voltage deviation and imbalanced power-sharing are discussed,and the selection principle of the control factor is proposed.Finally,the effectiveness of the proposed method is validated by the simulations on a five-terminal VSC based high-voltage direct current(VSC-HVDC)system.

一种低温度系数高阶补偿基准电压电路设计

基准电压对模拟系统的性能与精度有着至关重要的影响.一般的曲率补偿仅能消除与温度相关的二阶项,难以满足某些电路对高精度的要求.现有的电路存在温度系数较高的问题,亟须对更高阶进行补偿.本文提出了一种新的高阶曲率补偿方法,通过利用CMOS晶体管亚阈值特性设计,成功实现了一种低温度系数电压基准电路.该方法首先利用两个不同温度系数的电流流过相同的亚阈值区CMOS晶体管,产生两个具有不同温度特性的栅源电压.然后,通过对这两个不同温度特性的栅源电压进行相减,产生对数电压,并与一阶补偿电压进行加权叠加,从而实现高阶补偿.为了提高电源抑制比(PSRR),该电路采用了高增益负反馈回路,避免了传统电压基准电路中放大器的使用,进一步地降低了功耗.本设计基于0.18μm CMOS工艺,在Cadence软件下完成电路设计、版图设计与仿真验证.仿真结果显示,该电路正常工作电压范围为1.6~3 V,在2 V的工作电压下,基准电压输出295 mV,在-45~125℃范围内温度系数为1.26 ppm/℃,PSRR为51.1 dB@1 kHz,最大静态电流为8.9μA.结果表明,该基准电压电路能够满足高精度集成电路系统的需求.

模拟集成电路设计课程实验项目驱动式教学改革

基于高校模拟集成电路设计课程实验项目分散且教学目标不明确,缺乏系统性和工程应用性,提出了项目驱动式教学改革。以与企业合作的工程项目为基础设立实验项目,并分解成由易及难的多个实验题目,分阶段、分步骤完成实验内容,最终完成模拟集成电路设计全流程实验,以“带隙基准电压源芯片全定制设计实验”为例阐述了实施步骤。课程实验项目采用驱动式教学加深了学生对课程内容的理解,有助于培养学生扎实的工程实践能力。

附带STATCOM的HVDC系统改进参考电压控制法

在弱交流系统下对于附带有STATCOM的电网换相换流器高压直流输电(Line Commutated Converter based High Voltage Direct Current, LCC-HVDC)系统,存在着LCC逆变站与STATCOM之间耦合导致LCC-HVDC系统的稳定裕度下降问题,这会减弱LCC-HVDC抑制换相失败的能力。此外,HVDC控制环节之中的电压指令电流控制(voltage dependent current order limiter, VDCOL)环节的输出电流指令大幅剧烈波动还有几率会导致HVDC系统在首次换相失败之后发生后续换相失败。针对上述问题提出了一种“改进参考电压”的思想,对STATCOM和VDCOL的参考电压与输入电压分别进行修正。首先在STATCOM原本的参考电压经过一个“虚拟电抗”之后得到一个新的参考电压,通过这个改进参考电压弱化了STATCOM电压外环控制模块与LCC逆变站的耦合,减小了交流系统等效阻抗的大小,提升了系统对干扰的抵抗能力。然后对VDCOL的输入电压进行改进,新的改进输入电压改善了故障后VDCOL输出电流指令的大幅剧烈波动情况。最后通过三个层次的对照试验,验证了所提方法的有效性。

基于全连接神经网络的颅脑电阻抗成像参考电压预测方法

电阻抗层析成像(EIT)作为一种新兴可视化技术,可通过电导率分布变化的重建图像获得人体组织病理变化信息,为疾病检测提供了一种选择。在基于EIT的颅脑疾病检测中,为了准确获取差分成像图像重建所需的参考电压,提出一种基于全连接神经网络(FCNN)的参考电压预测方法。通过研究所提方法在不同信噪比情况下的图像重建性能,验证所提方法对参考电压预测的准确性和泛化能力。此外,还研究了头皮、颅骨和脑组织电导率分别发生变化时所提方法的有效性,并通过计算模糊半径和相关系数对图像重建质量进行了定量评价。结果表明,所提方法在一定电导率范围内和不同噪声水平下能够有效预测参考电压。

高增益高驱动能力的基准电压缓冲芯片的设计

为了解决当前CMOS基准电压缓冲器在驱动大电容负载电路时所面临的可靠性问题和性能瓶颈,提出一种高增益高驱动能力的基准电压缓冲芯片。该芯片采用CMOS缓冲放大器,结构包括折叠式共源共栅输入级、轨至轨Class AB输出级和推挽输出缓冲级。设计中加入了修调电路、Clamp电路及ESD防护电路。芯片面积为2390μm×1660μm。在SMIC 0.18μm CMOS工艺下进行了前仿真、版图绘制及Calibre后仿真。前仿结果显示:当负载电容为10μF时,电路实现了126 dB的高开环增益和97°的相位裕度,同时PSRR超过131 dB,噪声为448 nV/Hz@100 Hz及1 nV/Hz@100 Hz。后仿结果与前仿结果基本一致。总体结果表明,该电路具有高增益、高电源抑制比及低噪声等特点,同时拥有很高的输出驱动能力。因此,所提出的基准电压缓冲芯片可以用于驱动如像素阵列等具有大电容负载的电路。

基于光伏动态电流参考值的两级式光伏并网系统低电压穿越控制策略

随着光伏接入容量的不断提升,电网电压跌落时光伏脱网会影响系统稳定运行,因此光伏系统应具备低电压穿越(LVRT)能力。然而,目前常用的两级式光伏并网系统LVRT控制策略存在光伏动态响应慢及控制效果受限于光伏P–U特性曲线的数学模型精度等问题,且未考虑局部阴影条件下的适用性。基于此,提出一种基于光伏动态电流参考值的LVRT控制策略。首先,在建立两级式光伏并网系统及光伏电池P–U特性数学模型的基础上,分别对目前常用的基于定直流母线电压和基于光伏P–U特性曲线的LVRT控制的原理及不足进行了分析。其次,针对前级boost电路的控制构造了具有自适应收敛特性的光伏输出电流动态参考值以对光伏工作点进行直接调整。该策略无需对光伏P–U特性曲线数学模型进行求解,避免求解误差的同时加快了光伏动态响应速度。此外,在最大功率跟踪(MPPT)算法中引入故障解耦模块,在电网低电压故障期间对MPPT输出电压参考值进行锁定,避免MPPT无效运算带来的电压参考值偏移,使系统在故障结束时能以最快速度恢复至最大功率点。最后,通过仿真将所提策略与目前常用的基于定直流母线电压和基于光伏P–U特性曲线的LVRT控制策略在多种环境条件下进行对比。仿真结果表明:与定直流母线电压控制策略相比,所提策略下光伏动态响应快;与现有基于光伏P–U特性曲线的控制策略相比,所提策略不受P–U特性误差的影响,在辐照度变化尤其局部阴影条件下均能很好地实现低电压穿越。

一种宽输入范围高PSR带隙基准电路设计

从DC-DC芯片电路的实际设计需求出发,设计了一款输入电压范围在2.5~15 V的带隙基准电路。通过预调节电路的设计,带隙基准核输出的基准电压转化为一个稳定的电流源,形成的负反馈结构给带隙基准核自身提供供电电压,提高了电源电压范围上限;通过电压选择电路,在电源电压低于5 V时使带隙基准核直接由电源电压供电,拓宽了电源电压范围的下限。同时,预调节电路和带隙基准核中共源共栅结构为电路带来了良好的电源抑制特性。设计基于0.25μm BCD工艺,完成了原理图、版图设计以及仿真,结果表明设计在-55℃~125℃的温度范围内,可以输出稳定的0.8 V电压,温度系数为7.78 ppm/℃;低频条件下PSR达到159 dB,线性调整率为0.0012%。

软击穿对压控磁各向异性磁隧道结及其读电路性能影响

为了解决软击穿导致的压控磁各向异性磁隧道结(voltage-controlled magnetic anisotropy magnetic tunnel junction,VCMA-MTJ)及其读电路性能下降的问题,在对VCMA-MTJ软击穿机理深入分析的基础上,修正了VCMA-MTJ的电学模型,设计了一种具有固定参考电阻的VCMA-MTJ读电路和一种具有参考电阻调控单元的VCMA-MTJ读电路,研究了软击穿对VCMA-MTJ电阻R_(t)、隧穿磁阻比率M、软击穿时间T_(s)以及VCMA-MTJ读电路读错误率的影响。结果表明:软击穿的出现会导致R_(t)和M均随应力时间t的增加而降低,T_(s)随氧化层厚度t_(ox)的增大而缓慢增加,却随脉冲电压V_(b)的增大而迅速减少,与反平行态相比,平行态的T_(s)更短且M降低50%所需时间更少;具有固定参考电阻的VCMA-MTJ读电路可有效避免读“0”错误率的产生,但读“1”错误率却随t的增加而上升,而具有参考电阻调控单元的VCMA-MTJ读电路可在保持读“0”正确率的同时,对读“1”错误率改善达54%,在一定程度上削弱了软击穿对VCMA-MTJ读电路的影响。

一种高电源抑制比快速启动的带隙基准的设计

文章采用5 V、0.35μm CMOS工艺,设计一种适用于低噪声高速系统的带隙基准电压源电路。为了保证电路具有较高的电源抑制比(power supply rejection ratio,PSRR),设计一种抑制电源电压波动的负反馈回路,并且在电路中采用具有较高增益的两级放大器结构。针对某些系统快速启动的需求,设计快速启动电路,当电源上电时启动电路直接作用于基准电压,加速带隙基准电路的启动,在电路正常启动后通过开关管使启动电路停止工作。仿真结果表明,温度在-40~125℃范围内,带隙基准的温漂系数为13.05×10^(-6)℃^(-1);低频时PSRR为100.6 dB;线性调整率(line regulation,LNR)为0.024 mV/V;启动时间为4μs。

基于低电压与高PSRR的带隙电压基准源设计

阐述对低电压、高电源抑制比(PSRR)的带隙电压基准源设计,分析带隙电压基准源的特点,结合原电路设计的局限性,设计了低电压、高PSRR的带隙电压基准源电路结构。仿真分析表明,仿真的结果和理论分析结果保持一致,所设计电路在低压模拟电路以及数字信号处理系统中有较好适用性。

ISO 16750-2:2023中叠加交流电压测试解析与系统实现

叠加交流电压测试是汽车零部件电气负荷性能的重要检测项目之一,ISO 16750-2:2023对该测试扩充了测试频率并提出了限制电流的要求。文章从新旧标准的变化、测试内容、系统搭建和软件控制的逻辑等方面进行了分析,提出了采用变压器耦合法的系统实现方法,指出了实际应用中可能遇到的疑问,以期推动汽车及零部件生产企业提升测试方法的规范性,促进新能源汽车事业的发展。

高压交流断路器标准的主要差异分析

本文主要对GB/T 1984—2014与IEC 62271-100:2021的差异进行分析,主要针对文本差异和基本技术参量差异两个方面,其中文本差异主要分析了适用范围和规范性引用文件、使用条件以及术语和定义;基本技术参量差异主要分析了额定绝缘水平、温升限值、TRV参数以及试验参量的容差。通过以上几个方面的分析,加深对标准理解和规范检测认证。