On-Resistance Degradations Under Different Stress Conditions in High Voltage pLEDMOS Transistors and an Improved Method

The on-resistance degradations of the p-type lateral extended drain MOS transistor （pLEDMOS） with thick gate oxide under different hot carrier stress conditions are different, which has been experimentally investigated. This difference results from the interface trap generation and the hot electron injection, and trapping into the thick gate oxide and field oxide of the pLEDMOS transistor. An improved method to reduce the on-resistance degradations is also presented, which uses the field oxide as the gate oxide instead of the thick gate oxide. The effects are analyzed with a MEDICI simulator.

An Ultra-Low Specific On-Resistance VDMOS with a Step Oxide-Bypassed Trench Structure

A novel Step Oxide-Bypassed （SOB） trench VDMOS structure is designed based on the Oxide-Bypassed concept proposed by Liang Y C. This structure is suitable for breakdown voltage below 300V to obtain ultra-low specific on-resistance. The main feature of this structure is the various thicknesses of sidewall oxide,which modulate electric field distribution in the drift region and the charge compensation effect. As a result, the breakdown voltage is increased no less than 20% due to the more uniform electric field of the drift region,while the specific on-resistance was reduced by 40%-60% for the step oxide bypassed compared with the oxide-bypassed structure.

A low specific on-resistance SOI LDMOS with a novel junction field plate

A low specific on-resistance SO1 LDMOS with a novel junction field plate （JFP） is proposed and investigated theo- retically. The most significant feature of the JFP LDMOS is a PP-N junction field plate instead of a metal field plate. The unique structure not only yields charge compensation between the JFP and the drift region, but also modulates the surface electric field. In addition, a trench gate extends to the buffed oxide layer （BOX） and thus widens the vertical conduction area. As a result, the breakdown voltage （BV） is improved and the specific on-resistance （Ron,sp） is decreased significantly. It is demonstrated that the BV of 306 V and the Ron,sp of 7.43 mΩ.cm2 are obtained for the JFP LDMOS. Compared with those of the conventional LDMOS with the same dimensional parameters, the BV is improved by 34.8%, and the Ron,sp is decreased by 56.6% simultaneously. The proposed JFP LDMOS exhibits significant superiority in terms of the trade-off between BV and Ron,sp. The novel JFP technique offers an alternative technique to achieve high blocking voltage and large current capacity for power devices.

A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration

A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

Low specific on-resistance GaN-based vertical heterostructure field effect transistors with nonuniform doping superjunctions

A novel Ga N-based vertical heterostructure field effect transistor（HFET） with nonuniform doping superjunctions（non-SJ HFET） is proposed and studied by Silvaco-ATLAS,for minimizing the specific on-resistance（RonA） at no expense of breakdown voltage（BV）.The feature of non-SJ HFET lies in the nonuniform doping concentration from top to bottom in the n-and p-pillars,which is different from that of the conventional Ga N-based vertical HFET with uniform doping superjunctions（un-SJ HFET）.A physically intrinsic mechanism for the nonuniform doping superjunction（non-SJ） to further reduce RonA at no expense of BV is investigated and revealed in detail.The design,related to the structure parameters of non-SJ,is optimized to minimize the RonA on the basis of the same BV as that of un-SJ HFET.Optimized simulation results show that the reduction in RonA depends on the doping concentrations and thickness values of the light and heavy doping parts in non-SJ.The maximum reduction of more than 51% in RonA could be achieved with a BV of 1890 V.These results could demonstrate the superiority of non-SJ HFET in minimizing RonA and provide a useful reference for further developing the Ga N-based vertical HFETs.

Ultra-low specific on-resistance vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench（HK TG VDMOS） is proposed in this paper.The HK TG VDMOS features a high-k（HK） trench below the trench gate.Firstly,the extended HK trench not only causes an assistant depletion of the n-drift region,but also optimizes the electric field,which therefore reduces Ron,sp and increases the breakdown voltage（BV）.Secondly,the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration.Thirdly,compared with the superjunction（SJ） vertical double-diffused metal-oxide semiconductor（VDMOS）,the new device is simplified in fabrication by etching and filling the extended trench.The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation;its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%,in comparison with those of the conventional trench gate VDMOS（TG VDMOS） and conventional superjunction trench gate VDMOS（SJ TG CDMOS）.

Ultra-low specific on-resistance high-voltage vertical double diffusion metal–oxide–semiconductor field-effect transistor with continuous electron accumulation layer

A new ultra-low specific on-resistance （Ron,sp） vertical double diffusion metal-oxide-semiconductor field-effect tran- sistor （VDMOS） with continuous electron accumulation （CEA） layer, denoted as CEA-VDMOS, is proposed and its new current transport mechanism is investigated. It features a trench gate directly extended to the drain, which includes two PN junctions. In on-state, the electron accumulation layers are formed along the sides of the extended gate and introduce two continuous low-resistance current paths from the source to the drain in a cell pitch. This mechanism not only dramatically reduces the Ron,sp but also makes the Ron,sp almost independent of the n-pillar doping concentration （Am）. In off-state, the depletion between the n-pillar and p-pillar within the extended trench gate increases the Nn, and further reduces the Ron,sp. Especially, the two PNjunctions within the trench gate support a high gate--drain voltage in the off-state and on-state, re- spectively. However, the extended gate increases the gate capacitance and thus weakens the dynamic performance to some extent. Therefore, the CEA-VDMOS is more suitable for low and medium frequencies application. Simulation indicates that the CEA-VDMOS reduces the Ron,sp by 80% compared with the conventional super-junction VDMOS （CSJ-VDMOS） at the same high breakdown voltage （BV）.

Dual-gate lateral double-diffused metal—oxide semiconductor with ultra-low specific on-resistance

A new high voltage trench lateral double-diffused metal–oxide semiconductor （LDMOS） with ultra-low specific onresistance （R on,sp ） is proposed. The structure features a dual gate （DG LDMOS）： a planar gate and a trench gate inset in the oxide trench. Firstly, the dual gate can provide a dual conduction channel and reduce R on,sp dramatically. Secondly, the oxide trench in the drift region modulates the electric field distribution and reduces the cell pitch but still can maintain comparable breakdown voltage （BV）. Simulation results show that the cell pitch of the DG LDMOS can be reduced by 50% in comparison with that of conventional LDMOS at the equivalent BV; furthermore, R on,sp of the DG LDMOS can be reduced by 67% due to the smaller cell pitch and the dual gate.

Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal–oxide–semiconductor device with high-κ insulator

An improved vertical power double-diffused metal–oxide–semiconductor（DMOS） device with a p-region（P1） and high-κ insulator vertical double-diffusion metal–oxide–semiconductor（HKP-VDMOS） is proposed to achieve a better performance on breakdown voltage（BV）/specific on-resistance（Ron,sp） than conventional VDMOS with a high-κ insulator（CHK-VDMOS）.The main mechanism is that with the introduction of the P-region,an extra electric field peak is generated in the drift region of HKP-VDMOS to enhance the breakdown voltage.Due to the assisted depletion effect of this p-region,the specific on-resistance of the device could be reduced because of the high doping density of the N-type drift region.Meanwhile,based on the superposition of the depleted charges,a closed-form model for electric field/breakdown voltage is generally derived,which is in good agreement with the simulation result within 10% of error.An HKP-VDMOS device with a breakdown voltage of 600 V,a reduced specific on-resistance of 11.5 Ωm·cm^2 and a figure of merit（FOM）（BV^2/Ron,sp）of 31.2 MW·cm^-2 shows a substantial improvement compared with the CHK-VDMOS device.

Low on-resistance 1.2 kV 4H-SiC power MOSFET with Ron, sp of 3.4 mΩ·cm^2

A 4H-SiC power MOSFET with specific on-resistance of 3.4 mΩ·cm^2 and breakdown voltage exceeding 1.5 kV is designed and fabricated.Numerical simulations are carried out to optimize the electric field strength in gate oxide and at the surface of the semiconductor material in the edge termination region.Additional n-type implantation in JFET region is implemented to reduce the specific on-resistance.The typical leakage current is less than 1μA at VDS=1.4 kV.Drain–source current reaches 50 A at VDS=0.75 V and VGS=20 V corresponding to an on-resistance of 15 mΩ.The typical gate threshold voltage is 2.6 V.

Novel high- with low specific on-resistance high voltage lateral double-diffused MOSFET

A novel voltage-withstand substrate with high-K（HK, k 〉 3.9, k is the relative permittivity） dielectric and low specific on-resistance（Ron,sp） bulk-silicon, high-voltage LDMOS（HKLR LDMOS）is proposed in this paper. The high-K dielectric and highly doped interface N＋-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration（Nd） and reshape the electric field distribution. The highly doped N＋-layer under the high-K dielectric acts as a low resistance path to reduce the Ron,sp. The new device with the high breakdown voltage（BV）, the low Ron,sp, and the excellent figure of merit（FOM = BV^2/Ron,sp） is obtained. The BV of HKLR LDMOS is 534 V, Ron,sp is 70.6 m？·cm^2, and FOM is 4.039 MW·cm^（-2）.

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

A low specific on-resistance（Ron,sp） integrable silicon-on-insulator（SOI） metal-oxide semiconductor field-effect transistor（MOSFET） is proposed and investigated by simulation.The MOSFET features a recessed drain as well as dual gates,which consist of a planar gate and a trench gate extended to the buried oxide layer（BOX）（DGRD MOSFET）.First,the dual gates form dual conduction channels,and the extended trench gate also acts as a field plate to improve the electric field distribution.Second,the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path.Third,the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions.All of these sharply reduce Ron,sp and maintain a high breakdown voltage（BV）.The BV of 233 V and Ron,sp of 4.151 mΩ·cm2（VGS = 15 V） are obtained for the DGRD MOSFET with 15-μm half-cell pitch.Compared with the trench gate SOI MOSFET and the conventional MOSFET,Ron,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV,respectively.The trench gate extended to the BOX synchronously acts as a dielectric isolation trench,simplifying the fabrication processes.

An ultra-low specific on-resistance trench LDMOS with a U-shaped gate and accumulation layer

An ultra-low specific on-resistance （Ron,sp） oxide trench-type silicon-on-insulator （SOI） lateral double-diffusion metal-oxide semiconductor （LDMOS） with an enhanced breakdown voltage （BV） is proposed and investigated by simulation. There are two key features in the proposed device： one is a U-shaped gate around the oxide trench, which extends from source to drain （UG LDMOS）; the other is an N pillar and P pillar located in the trench sidewall. In the on-state, electrons accumulate along the U-shaped gate, providing a continuous low resistance current path from source to drain. The Ron,sp is thus greatly reduced and almost independent of the drift region doping concentration. In the off-state, the N and P pillars not only enhance the electric field （E-field） strength of the trench oxide, but also improve the E-field distribution in the drift region, leading to a significant improvement in the BV. The BV of 662 V and Ron,sp of 12.4 mΩ.cm2 are achieved for the proposed UG LDMOS. The BV is increased by 88.6% and the Ron,sp is reduced by 96.4%, compared with those of the conventional trench LDMOS （CT LDMOS）, realizing the state-of-the-art trade-off between BV and Ron,sp.

Ultralow Specific on-Resistance Trench MOSFET with a U-Shaped Extended Gate

An ultralow specific on-resistance （Ron,sp） trench metal-oxide-semiconductor field effect transistor （MOSFET） with an improved off-state breakdown voltage （BV） is proposed. It features a U-shaped gate around the drift region and an oxide trench inserted in the drift region （UG MOSFET）. In the on-state, the U-shaped gate induces a high density electron accumulation layer along its sidewall, which provides a low-resistance current path from the source to the drain, realizing an ultralow Ron,sp. The value of Ron,sp is almost independent of the drift doping concentration, and thus the UG MOSFET breaks through the contradiction relationship between R p and the off-state BV. Moreover, the oxide trench folds the drift region, enabling the UG MOSFET to support a high BV with a shortened cell pitch. The UG MOSFET achieves an Ron,sp of 2 mΩ·cm^2 and an improved BV of 216 V, superior to the best existing state-of-the-art transistors at the same BV level

A Novel Interface-Gate Structure for SOI Power MOSFET to Reduce Specific On-Resistance

A novel silicon-on-insulator （SOI） power metM-oxide-semiconductor field effect transistor with an interface-gate （IG SOI） structure is proposed, in which the trench polysificon gate extends into the buried oxide layer （BOX） at the source side and an IG is formed. Firstly, the IG offers an extra accumulation channel for the carriers. Secondly, the subsidiary depletion effect of the IG results in a higher impurity doping for the drift region. A low specific on-resistance is therefore obtained under the condition of a slightly enhanced breakdown voltage for the IG SOI. The influences of structure parameters on the device performances are investigated. Compared with the conventional trench gate SOI and lateral planar gate SOI, the specific on-resistances of the IG SOI are reduced by 36.66% and 25.32% with the breakdown voltages enhanced by 2.28% and 10.83% at the same SOI layer of 3 μm, BOX of 1 μm, and half-cell pitch of 5.5 μm, respectively.

A novel structure in reducing the on-resistance of a VDMOS

A novel structure of a VDMOS in reducing on-resistance is proposed. With this structure, the specific on-resistance value of the VDMOS is reduced by 22% of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory, and there is only one additional mask in processing the new structure VDMOS, which is easily fabricated. With the TCAD tool, one 200 V N-channel VDMOS with the new structure is analyzed, and simulated results show that a specific on-resistance value will reduce by 23%, and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers. The novel structure can be widely used in the strip-gate VDMOS area.

Ultralow specific ON-resistance high-k LDMOS with vertical field plate

An ultralow specific on-resistance high-k LDMOS with vertical field plate（VFP HK LDMOS） is proposed. The high-k dielectric trench and highly doped interface N＋ layer are made in bulk silicon to reduce the surface field of the drift region in the VFP HK LDMOS. The gate vertical field plate（VFP） pinning in the high-k dielectric trench can modulate the bulk electric field. The high-k dielectric not only provides polarized charges to assist depletion of the drift region, so that the drift region and high-k trench maintain charge balance adaptively,but also can fully assist in depleting the drift region to increase the drift doping concentration and reshape the electric field to avoid premature breakdown. Compared with the conventional structure, the VFP HK LDMOS has the breakdown voltage of 629.1 V at the drift length of 40 μm and the specific on-resistance of 38.4 mΩ·cm^2 at the gate potential of 15 V. Then the power figure of merit is 10.31 MW/cm^2.

A low on-resistance SOI LDMOS using a trench gate and a recessed drain

An integrable silicon-on-insulator （SOl） power lateral MOSFET with a trench gate and a recessed drain （TGRD MOSFET） is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide （BOX） and the recessed drain reduce the specific on-resistance （Ron, sp） by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage （BV） of 97 V and Ron, sp of 0.985 mf2-cm2 （l/os = 5 V） are obtained for a TGRD MOSFET with 6.5/xm half-cell pitch. Compared with the trench gate SOI MOSFET （TG MOSFET） and the conventional MOSFET, Ron＇ sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain （TGTD MOSFET）, BV of the TGRD MOSFET increases by 37% at the same Ron,sp.

Design of 700 V triple RESURF nLDMOS with low on-resistance

A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ.cm^2 is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.

Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect

A RESURF-enhanced high voltage SOl LDMOS （ER-LDMOS） with an ultralow specific on-resistance （Ron, sp） is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer （BPL） under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension （JTE）, but also forms a vertical reduced surface field （RESURF） structure with the N- drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer （BOX） exhibits a triple- RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage （BV） and a low Ron, sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron, sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron, sp by 91% compared with the conventional trench LDMOS at the same cell pitch.