Symbolic Macromodeling for Statistical Simulation of Operational Amplifiers

Symbolic circuit simulator is traditionally applied to the small-signal analysis of analog circuits. This paper establishes a symbolic behavioral macromodeling method applicable to both small-signal and large-signal analysis of general two-stage operational amplifiers （op-amps）. The proposed method creates a two-pole parametric macromodel whose parameters are analytical functions of the circuit element parameters generated by a symbolic circuit simulator. A moment matching technique is used in deriving the analytical model parameter. The created parametric behavioral model can be used for op-amps performance simulation in both frequency and time domains. In particular, the parametric models are highly suited for fast statistical simulation of op-amps in the time-domain. Experiment results show that the statistical distributions of the op-amp slew and settling time characterized by the proposed model agree well with the transistor-level results in addition to achieving significant speedup.

Annealing behavior of radiation damage in JFET-input operational amplifiers

The elevated and room temperature annealing behavior of radiation damage in JFET-input operational amplifiers （op-amps） were investigated. High- and low-dose-rate irradiation results show that one of the JFET-input op-amps studied in this paper exhibits enhanced low-dose-rate sensitivity and the other shows time-dependent effect. The offset voltage of both op-amps increases during long-term annealing at room temperature. However, the offset voltage decreases at elevated temperature. The dramatic difference in annealing behavior at room and elevated temperatures indicates the migration behavior of radiation-induced species at elevated and room temperatures. This provides useful information to understand the degradation and annealing mechanisms in JFET-input op-amps under total ionizing radiation. Moreover, the annealing of oxide trapped charges should be taken into consideration, when using elevated temperature methods to evaluate low-dose-rate damage.

Design procedure for optimizing CMOS low noise operational amplifiers

This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier. The design procedure focuses on the noise performance, which is the key requirement for low noise operational amplifiers. Based on the noise level and other specifications such as bandwidth, signal swing, slew rate, and power consumption, the device sizes and the biasing conditions are derived. In order to verify the proposed design procedure, a three-stage operational amplifier has been designed. The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.

A low-powerlow-voltage slew-rate enhancement circuit for two-stage operational amplifiers

A novel circuit is presented in order to enhance the slew rate of two-stage operational amplifiers. The enhancer utilizes the class-AB input stage to improve current efficiency, while it works on an open loop with regard to the enhanced amplifier so that it has no effect on the stability of the amplifier. During the slewing period, the enhancer detects input differential voltage of the amplifier, and produces external enhancement currents for the amplifier, driving load capacitors to charge/discharge faster. Simulation results show that, fora large input step, the enhancerreduces settling time by nearly 50%. When the circuit is employed in a sample-and-hold circuit, it greatly improves the spur-free dynamic range by 44.6 dB and the total harmonic distortion by 43.9 dB. The proposed circuit is very suitable to operate under a low voltage （1.2 V or below） with a standby current of 200 μA.

Active Damping of Milling Vibration Using Operational Amplifier Circuit

The problem of chatter vibration is associated with adverse consequences that often lead to tool impairment and poor surface finished in a workpiece, and thus, controlling or suppressing chatter vibrations is of great significance to improve machining quality. In this paper, a workpiece and an actuator dynamics are considered in modeling and controller design. A proportional-integral controller(PI) is presented to control and actively damp the chatter vibration of a workpiece in the milling process. The controller is chosen on the basis of its highly stable output and a smaller amount of steady-state error. The controller is realized using analog operational amplifier circuit. The work has contributed to planning a novel approach that addresses the problem of chatter vibration in spite of technical hitches in modeling and controller design. The method can also lead to considerable reduction in vibrations and can be beneficial in industries in term of cost reduction and energy saving. The application of this method is verified using active damping device actuator(ADD) in the milling of steel.

Low-Power Operational Amplifier for Real-Time Signal Processing System of Micro Air Vehicle

A low-power complementary metal oxide semiconductor（CMOS） operational amplifier （op-amp） for real-time signal processing of micro air vehicle （MAV） is designed in this paper.Traditional folded cascode architecture with positive channel metal oxide semiconductor（PMOS） differential input transistors and sub-threshold technology are applied under the low supply voltage.Simulation results show that this amplifier has significantly low power,while maintaining almost the same gain,bandwidth and other key performances.The power required is only 0.12 mW,which is applicable to low-power and low-voltage real-time signal acquisition and processing system.

Efficient Slew-Rate Enhanced Operational Transconductance Amplifier

Today, along with the prevalent use of portable equipment, wireless, and other battery powered systems, the demand for amplifiers with a high gain-bandwidth product（GBW）, slew rate（SR）, and at the same time very low static power dissipation is growing. In this work, an operational transconductance amplifier（OTA） with an enhanced SR is proposed. By inserting a sensing resistor in the input port of the current mirror in the OTA, the voltage drop across the resistor is converted into an output current containing a term in proportion to the square of the voltage, and then the SR of the proposed OTA is significantly enhanced and the current dissipation can be reduced. The proposed OTA is designed and simulated with a 0.5μm complementary metal oxide semiconductor（CMOS） process. The simulation results show that the SR is 4.54V/μs, increased by 8.25 times than that of the conventional design, while the current dissipation is only 87.3%.

Fully-Differential Multichannel Integrated Neural Signal Recording Front-End

Neural signal can be used for clinical disease diagnosis,data analysis and real-time life signal monitoring.Its analysis requires high-performance signal processors.Based on the 180 nm standard CMOS technology,a16-channel fully-differential neural recording chip is designed.The chip consists of 16-channel low-noise pre-amplifiers,a multiplexer and a successive approximation register（SAR）ADC.The result shows that the equivalent input-referred noise of recording amplifier is 3.63μV,bringing down noise efficiency factor to 4.24.At 8.5 bits effective number of bit（ENOB）,the analog-to-digital converter（ADC）has an SNR of 52.6dB.The core area of the proposed neural recording front-end is about 2.46 mm^2.

Simple Simulated Inductor, Low-Pass/Band-Pass Filter and Sinusoidal Oscillator Using OTRA

Although a variety of applications of the OTRAs have been reported in literature, the pole of the transresistance gain Rm of the OTRA has been usually considered to affect the performance of the circuits due to being parasitic. In this paper, the pole of the OTRA has been used to evolve some simple OTRA-based active-R circuits for realizing a synthetic inductor, single resistance controlled oscillator and low-pass/band-pass filter. The workability of all the proposed circuits has been verified by SPICE simulations and all the new circuits have been found to work as predicted by theory. The exemplary propositions suggest that it is worthwhile to further investigate new circuit designs using OTRA-pole.

国外模拟集成电路近期发展动态

近年来,由于器件工艺水平的提高和电路设计技术的改进,模拟集成电路获得了很大的发展。席卷世界先进工业国家的三“A”革命(工厂自动化、办公室自动化和家庭自动化)和各种高精尖的军事装备,使品种繁多的模拟电路找到了用武之地。目前,国外半导体厂家正在竞相开发新的品种,并且不断扩大其应用范围,本文拟对应用比较广泛的几种主要模拟集成电路在国外的发展情况作一简单介绍。

DOCCII-based electronically tunable current-mode biquadratic filters

A complete state variable current-mode biquadratic filter built by duo-output CCII (DOCCII) with variable current gain is presented. All the coefficients of the filter can be independently tuned through the variable current gain factors of the DOCCII. Based on the principles upon which the general biquadratic filter was constructed, a universal electronically tunable current-mode filter is proposed which implements the low-pass, high-pass, band-pass, band-suppress and all-pass second order transfer functions simultaneously. The PSPICE simulations of frequency responses of second-order filter of are also given.

CMOS Realization of VDVTA and OTA Based Fully Electronically Tunable First Order All Pass Filter with Optimum Linearity at Low Supply Voltage ±0.85 V

This paper presents a new first order all pass filter configurations. The proposed all pass filter configuration employs two configurations namely VDVTA and OTAs based first order all pass filter configuration. The first proposed configuration employs a single VDVTA and one grounded capacitor whereas the second proposed configuration employs two OTAs and one grounded capacitor. Both types of proposed configurations are fully electronically tunable and their quality factors do not depend on tunable pole frequency range. The reported configurations yield low active and passive sensitivities and also have low power consumption with very low supply voltage ± 0.85 V with Bias Voltage ± 0.50 V. The PSPICE simulation of the proposed VDVTA and two OTAs based first order all pass filter configurations are verified using 0.18 μm CMOS Technology Process Parameters.

CFOA Based Band Pass and Band Stop Ladder Filter—A New Configuration

A new technique for the conversion of ladder based filter into CFOA based filter has been proposed. The technique uses signal flow graph and converts the existing LC ladder based filter into band pass & band stop configurations. The design of band pass and band stop filter has been realized using the proposed technique. The proposed configuration is implemented using CFOA as an active device and all the capacitors are grounded. CFOA based circuits have greater linearity, high dynamic rate, high slew rate and high signal bandwidth. Simulation has been carried out using simulation software P Spice (v10.1). The simulation results have been demonstrated and discussed.

New Single Input Multiple Output Type Current Mode Biquad Filter Using OTAs

This paper presents a new current mode (CM) single-input and multi-output (SIMO)-type biquad using two multiple output OTAs and one current follower as an active device and having two grounded capacitors. This SIMO type circuit realizes all the five filter functions as low pass, band pass, high pass, band reject and all pass filter transfer functions simultaneously. This circuit has the unity gain transfer function for all the five types of filters. The circuit enjoys electronic tunability of angular frequency and bandwidth. The 0.18 μm TSMC technology process parameters have been utilized to test and verify the performance characteristics of the circuit using PSPICE. The sensitivity analysis, transient response and calculations of total harmonic distortion have also been shown.

A Process Variation Tolerant OTA Design for Low Power ASIC Design

Technology development and continuous down scaling in CMOS fabrication makes Mixed Signal Integrated Circuits (MSIC) more vulnerable to process variation. This paper presents a well defined novel design methodology for process variability aware design by incorporating the major challenge of statistical circuit performance relating the device and circuit level variation in an accurate and efficient manner to improve the reliability, robustness and stability of the circuit. The device sensitive parameters are identified and accurately quantified by continuous realistic assessments using statistical methods. The modularity of the methodology can be validated by the output performance obtained from the gain and phase response of OTA which is highly stable when subjected to worst case process variation scenario. In the proposed optimization, the circuit is strengthened by fixing the optimum aspect ratio without adding any additional compensation devices complicating the circuit resulting in low power consumption of only 0.116 mW in standard CMOS 0.18 μm technology with 1.8 V power supply.

A constant-g_m and high-slew-rate operational amplifier for an LCD driver

To drive the backplane of a liquid crystal display device and achieve different kinds of grey levels, a high-slew-rate operational amplifier with constant-gin input stage is presented. A Zener-diode structure is inserted between the tails of the complementary input pairs to keep the grn of the input stage constant. A novel slew rate enhancement circuit is implemented to achieve a very high slew rate. The chip has been implemented in a 0.5μm CMOS process and the chip area of the operational amplifier circuit is 0.11 mm^2. The testing results indicate that in the 5-8 V input range, the maximum gm fluctuation is only 4.2%. The result exhibits a high slew rate of 111 V/μs and 102 V/μs for the rising and falling edges under a 20 pF capacitance load, and the low frequency gain is up to 109 dB with a phase margin of 70 ℃.

A 12-bit,40-Ms/s pipelined ADC with an improved operational amplifier

This paper proposes a 12-bit,40-Ms/s pipelined analog-to-digital converter（ADC） with an improved high-gain and wide-bandwidth operational amplifier（opamp）.Based on the architecture of the proposed ADC,the non-ideal factors of opamps are first analyzed,which have the significant impact on the ADC＇s resolution.Then,the compensation techniques of the ADC＇s opamp are presented to restrain the negative effect introduced by the gainboosting technique and switched-capacitor common-mode-feedback structure.After analysis and optimization,the ADC implemented in a 0.35μm standard CMOS process shows a maximum signal-to-noise distortion ratio of 60.5 dB and a spurious-free dynamic range of 74.5 dB,respectively,at a 40 MHz sample clock with over 2 Vpp input range.

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper,capable of operating with minimum supply voltage at1 V.A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current,which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier.A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted,which not only improves the sense window enhancing read precision but also saves power consumption.The sense amplifier was implemented in a flash realized in 90 run flash technology.Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125℃.

Design of a high-performance PJFET for the input stage of an integrated operational amplifier

With Shockley＇s approximate-channel theory and TCAD tools, a high-voltage, ultra-shallow junction PJFET for the input stage of an integrated operational amplifier （OPA） was realized. The high-performance PJFET device was developed in the Bi-FET process technology. The measured specifications are as follows. The top-gate junction depth is about 0.1 μm, the gate-leakage current is less than 5 pA, the breakdown voltage is more than 80 V, and the pinch-off voltage is optional between 0.8 and 2.0 V. The device and its Bi-FET process technology were used to design and process a high input-impedance integrated OPA. The measured results show that the OPA has a bias current of less than 50 pA, voltage noise of less than 50 nV/Hz^1/2, and current noise of less than 0.05 pA/Hz^1/2.

A novel low-voltage operational amplifier for low-power pipelined ADCs

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.