Efficient Virtual Network Embedding Algorithm Based on Restrictive Selection and Optimization Theory Approach

Network virtualization(NV) is widely considered as a key component of the future network and promises to allow multiple virtual networks(VNs) with different protocols to coexist on a shared substrate network(SN). One main challenge in NV is virtual network embedding(VNE). VNE is a NPhard problem. Previous VNE algorithms in the literature are mostly heuristic, while the remaining algorithms are exact. Heuristic algorithms aim to find a feasible embedding of each VN, not optimal or sub-optimal, in polynomial time. Though presenting the optimal or sub-optimal embedding per VN, exact algorithms are too time-consuming in smallscaled networks, not to mention moderately sized networks. To make a trade-off between the heuristic and the exact, this paper presents an effective algorithm, labeled as VNE-RSOT(Restrictive Selection and Optimization Theory), to solve the VNE problem. The VNERSOT can embed virtual nodes and links per VN simultaneously. The restrictive selection contributes to selecting candidate substrate nodes and paths and largely cuts down on the number of integer variables, used in the following optimization theory approach. The VNE-RSOT fights to minimize substrate resource consumption and accommodates more VNs. To highlight the efficiency of VNERSOT, a simulation against typical and stateof-art heuristic algorithms and a pure exact algorithm is made. Numerical results reveal that virtual network request(VNR) acceptance ratio of VNE-RSOT is, at least, 10% higher than the best-behaved heuristic. Other metrics, such as the execution time, are also plotted to emphasize and highlight the efficiency of VNE-RSOT.

A HIGH-PERFORMANCE VLSI ARCHITECTURE OF EBCOT BLOCK CODING IN JPEG2000

The paper presents a new architecture composed of bit plane-parallel coder for Embedded Block Coding with Optimized Truncation (EBCOT) entropy encoder used in JPEG2000. In the architecture, the coding information of each bit plane can be obtained simultaneously and processed parallel. Compared with other architectures, it has advantages of high parallelism, and no waste clock cycles for a single point. The experimental results show that it reduces the processing time about 86% than that of bit plane sequential scheme. A Field Programmable Gate Array (FPGA) prototype chip is designed and simulation results show that it can process 512×512 gray-scaled images with more than 30 frames per second at 52MHz.

State Prediction of Chaotic System Based on ANN Model

The choice of time delay and embedding dimension is very important to the phase space reconstruction of any chaotic time series. In this paper, we determine optimal time delay by computing autocorrelation function of time series. Optimal embedding dimension is given by means of the relation between embedding dimension and correlation dimension of chaotic time series. Based on the methods above, we choose ANN model to appoximate the given true system. At the same time, a new algorithm is applied to determine the network weights. At the end of this paper, the theory above is demonstrated through the research of time series generated by Logistic map.