Impact of Native Defects in the High Dielectric Constant Oxide HfSiO_4 on MOS Device Performance

Native dejects in HfSiO4 are investigated by first principles calculations. Transition levels of native detects can be accurately described by employing the nonlocal HSE06 hybrid functional. This methodology overcomes the band gap problem in traditional functionals. By band alignments among the Si, GaAs and HfSiO4. we are able to determine the position of defect levels in Si and GaAs relative to the HfSiO4 band gap. We evaluate the. possibility of these defects acting as fixed charge. Native defects lead to the change of valence and conduction band offsets. Gate leakage current is evaluated by the band offset. In addition, we also investigate diffusions of native defects, and discuss how they affect the MOS device performance.

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal–oxide–semiconductor devices

The effect of nitric oxide（NO） annealing on charge traps in the oxide insulator and transition layer in n-type4H–Si C metal–oxide–semiconductor（MOS） devices has been investigated using the time-dependent bias stress（TDBS）,capacitance–voltage（C–V）,and secondary ion mass spectroscopy（SIMS）.It is revealed that two main categories of charge traps,near interface oxide traps（Nniot） and oxide traps（Not）,have different responses to the TDBS and C–V characteristics in NO-annealed and Ar-annealed samples.The Nniotare mainly responsible for the hysteresis occurring in the bidirectional C–V characteristics,which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor.However,Not is mainly responsible for the TDBS induced C–V shifts.Electrons tunneling into the Not are hardly released quickly when suffering TDBS,resulting in the problem of the threshold voltage stability.Compared with the Ar-annealed sample,Nniotcan be significantly suppressed by the NO annealing,but there is little improvement of Not.SIMS results demonstrate that the Nniotare distributed within the transition layer,which correlated with the existence of the excess silicon.During the NO annealing process,the excess Si atoms incorporate into nitrogen in the transition layer,allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of Nniot.

Recent progress of Ga_(2)O_(3)materials and devices based on the low-cost,vacuum-free Mist-CVD epitaxial growth method

Compared with silicon,gallium nitride,silicon carbide,and other traditional semiconductors,gallium oxide(Ga_(2)O_(3))who possesses,an ultrawide bandgap of approximately 5.0 eV and a higher breakdown field strength of approximately 8 MV/cm has attracted increasing attention from researchers,especially for the potential application in power devices.Moreover,Ga_(2)O_(3)material has natural ultraviolet detection ability for photodetectors due to its ultrawide bandgap.These future commercial applications put forward an urgent require for high-quality epitaxial Ga_(2)O_(3)material in an efficient growth method at a lower cost.Although there are some conventional methods for single crystal Ga_(2)O_(3)film epitaxial growth such as MBE and MOCVD,these methods always need a vacuum growth environment and expensive equipment.As a fast-growing method,Mist-CVD gives the growth of Ga_(2)O_(3)in a vacuum-free,process-simple,and low-cost method,which will greatly reduce the cost and facilitate the development of Ga_(2)O_(3).This review has summarizes the Mist-CVD epitaxy growth mechanism of Ga_(2)O_(3),recent progress in the Ga_(2)O_(3)film epitaxial growth,and various device properties based on the Mist-CVD method.Our work aims to provide help for the development of Ga_(2)O_(3)material growth and device applications.

Investigation of Gate Defects in Ultrathin MOS Structures Using DTRS Technique

s:A detailed description of relaxation spectroscopy technique under direct tunneling stress is given.A double peak phenomena by applied relaxation spectroscopy on ultra thin (<3nm) gate oxide is found.It suggests that two kinds of traps exist in the degradation of gate oxide.It is also observed that both the trap density and the generation/capture cross section of oxide trap and interface trap are smaller in ultra thin gate oxide (<3nm) under DT stress than those in the thicker oxide (>4nm) under FN stress,and the centroid of oxide trap is closer to anode interface than in the center of oxide.

Multi-terminal pectin/chitosan hybrid electrolyte gated oxide neuromorphic transistor with multi-mode cognitive activities

In order to fulfill the urgent requirements of functional products,circuit integration of different functional devices are commonly utilized.Thus,issues including production cycle,cost,and circuit crosstalk will get serious.Neuromorphic computing aims to break through the bottle neck of von Neumann architectures.Electronic devices with multi-operation modes,especially neuromorphic devices with multi-mode cognitive activities,would provide interesting solutions.Here,pectin/chitosan hybrid electrolyte gated oxide neuromorphic transistor was fabricated.With extremely strong proton related interfacial electric-double-layer coupling,the device can operate at low voltage of below 1 V.The device can also operate at multi-operation mode,including bottom gate mode,coplanar gate and pseudo-diode mode.Interestingly,the artificial synapse can work at low voltage of only 1 mV,exhibiting extremely low energy consumption of~7.8 fJ,good signal-to-noise ratio of~229.6 and sensitivity of~23.6 dB.Both inhibitory and excitatory synaptic responses were mimicked on the pseudo-diode,demonstrating spike rate dependent plasticity activities.Remarkably,a linear classifier is proposed on the oxide neuromorphic transistor under synaptic metaplasticity mechanism.These results suggest great potentials of the oxide neuromorphic devices with multi-mode cognitive activities in neuromorphic platform.

Review of recent progresses on flexible oxide semiconductor thin film transistors based on atomic layer deposition processes

The current article is a review of recent progress and major trends in the field of flexible oxide thin film transistors（TFTs）, fabricating with atomic layer deposition（ALD） processes. The ALD process offers accurate controlling of film thickness and composition as well as ability of achieving excellent uniformity over large areas at relatively low temperatures. First, an introduction is provided on what is the definition of ALD, the difference among other vacuum deposition techniques, and the brief key factors of ALD on flexible devices. Second, considering functional layers in flexible oxide TFT, the ALD process on polymer substrates may improve device performances such as mobility and stability, adopting as buffer layers over the polymer substrate, gate insulators, and active layers. Third, this review consists of the evaluation methods of flexible oxide TFTs under various mechanical stress conditions. The bending radius and repetition cycles are mostly considering for conventional flexible devices. It summarizes how the device has been degraded/changed under various stress types（directions）. The last part of this review suggests a potential of each ALD film, including the releasing stress, the optimization of TFT structure, and the enhancement of device performance. Thus, the functional ALD layers in flexible oxide TFTs offer great possibilities regarding anti-mechanical stress films, along with flexible display and information storage application fields.